prev_cmp_uarttest.tan.qmsg

FPGA模拟UART

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "COUNT4:inst3\|SYNTHESIZED_WIRE_2_synthesized_var " "Info: Detected ripple clock \"COUNT4:inst3\|SYNTHESIZED_WIRE_2_synthesized_var\" as buffer" {  } { { "COUNT4.vhd" "" { Text "D:/TMP/UartTest/COUNT4.vhd" 63 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "COUNT4:inst3\|SYNTHESIZED_WIRE_2_synthesized_var" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var " "Info: Detected ripple clock \"COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var\" as buffer" {  } { { "COUNT4.vhd" "" { Text "D:/TMP/UartTest/COUNT4.vhd" 63 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74164:inst70\|3 " "Info: Detected ripple clock \"74164:inst70\|3\" as buffer" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "74164:inst70\|3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "RXD " "Info: No valid register-to-register data paths exist for clock \"RXD\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_PATH_NOT_FOUND" "Clock BaudRateMul4 74164:inst70\|3 " "Info: Can't find any paths of type Clock between source node \"BaudRateMul4\" and destination node \"74164:inst70\|3\"" {  } {  } 0 0 "Can't find any paths of type %1!s! between source node \"%2!s!\" and destination node \"%3!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "BaudRateMul4 register 74164:inst70\|3 register inst19 45.87 MHz 21.8 ns Internal " "Info: Clock \"BaudRateMul4\" has Internal fmax of 45.87 MHz between source register \"74164:inst70\|3\" and destination register \"inst19\" (period= 21.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.700 ns + Longest register register " "Info: + Longest register to register delay is 2.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74164:inst70\|3 1 REG LC34 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 19; REG Node = '74164:inst70\|3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74164:inst70|3 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.500 ns) 2.700 ns inst19 2 REG LC3 1 " "Info: 2: + IC(1.200 ns) + CELL(1.500 ns) = 2.700 ns; Loc. = LC3; Fanout = 1; REG Node = 'inst19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { 74164:inst70|3 inst19 } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1328 1096 1160 1408 "inst19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 55.56 % ) " "Info: Total cell delay = 1.500 ns ( 55.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 44.44 % ) " "Info: Total interconnect delay = 1.200 ns ( 44.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { 74164:inst70|3 inst19 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { 74164:inst70|3 {} inst19 {} } { 0.000ns 1.200ns } { 0.000ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.200 ns - Smallest " "Info: - Smallest clock skew is -6.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BaudRateMul4 destination 1.600 ns + Shortest register " "Info: + Shortest clock path from clock \"BaudRateMul4\" to destination register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns BaudRateMul4 1 CLK PIN_43 13 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'BaudRateMul4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { BaudRateMul4 } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 320 432 600 336 "BaudRateMul4" "" } { 1512 1160 1304 1528 "BaudRateMul4" "" } { 1896 912 1014 1912 "BaudRateMul4" "" } { 272 432 736 288 "BaudRateMul4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns inst19 2 REG LC3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC3; Fanout = 1; REG Node = 'inst19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { BaudRateMul4 inst19 } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1328 1096 1160 1408 "inst19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { BaudRateMul4 inst19 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { BaudRateMul4 {} BaudRateMul4~out {} inst19 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { BaudRateMul4 inst19 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { BaudRateMul4 {} BaudRateMul4~out {} inst19 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1328 1096 1160 1408 "inst19" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1328 1096 1160 1408 "inst19" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { 74164:inst70|3 inst19 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { 74164:inst70|3 {} inst19 {} } { 0.000ns 1.200ns } { 0.000ns 1.500ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { BaudRateMul4 inst19 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { BaudRateMul4 {} BaudRateMul4~out {} inst19 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "BaudRateMul4 16 " "Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock \"BaudRateMul4\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_PATH_NOT_FOUND" "Clock BaudRateMul4 74164:inst69\|10 " "Info: Can't find any paths of type Clock between source node \"BaudRateMul4\" and destination node \"74164:inst69\|10\"" {  } {  } 0 0 "Can't find any paths of type %1!s! between source node \"%2!s!\" and destination node \"%3!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "74164:inst69\|9 74164:inst69\|10 BaudRateMul4 3.6 ns " "Info: Found hold time violation between source  pin or register \"74164:inst69\|9\" and destination pin or register \"74164:inst69\|10\" for clock \"BaudRateMul4\" (Hold time is 3.6 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.200 ns + Largest " "Info: + Largest clock skew is 6.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BaudRateMul4 source 4.700 ns - Shortest register " "Info: - Shortest clock path from clock \"BaudRateMul4\" to source register is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns BaudRateMul4 1 CLK PIN_43 13 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'BaudRateMul4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { BaudRateMul4 } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 320 432 600 336 "BaudRateMul4" "" } { 1512 1160 1304 1528 "BaudRateMul4" "" } { 1896 912 1014 1912 "BaudRateMul4" "" } { 272 432 736 288 "BaudRateMul4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 2.300 ns COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var 2 REG LC11 10 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 2.300 ns; Loc. = LC11; Fanout = 10; REG Node = 'COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var } "NODE_NAME" } } { "COUNT4.vhd" "" { Text "D:/TMP/UartTest/COUNT4.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.200 ns) 4.700 ns 74164:inst69\|9 3 REG LC24 2 " "Info: 3: + IC(1.200 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC24; Fanout = 2; REG Node = '74164:inst69\|9'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|9 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 776 360 424 856 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 74.47 % ) " "Info: Total cell delay = 3.500 ns ( 74.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 25.53 % ) " "Info: Total interconnect delay = 1.200 ns ( 25.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { BaudRateMul4 {} BaudRateMul4~out {} COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var {} 74164:inst69|9 {} } { 0.000ns 0.000ns 0.000ns 1.200ns } { 0.000ns 1.000ns 1.300ns 1.200ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { BaudRateMul4 {} BaudRateMul4~out {} COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var {} 74164:inst69|9 {} } { 0.000ns 0.000ns 0.000ns 1.200ns } { 0.000ns 1.000ns 1.300ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns - " "Info: - Micro clock to output delay of source is 0.700 ns" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 776 360 424 856 "9" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.500 ns - Shortest register register " "Info: - Shortest register to register delay is 2.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74164:inst69\|9 1 REG LC24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC24; Fanout = 2; REG Node = '74164:inst69\|9'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74164:inst69|9 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 776 360 424 856 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.500 ns) 2.500 ns 74164:inst69\|10 2 REG LC40 2 " "Info: 2: + IC(1.000 ns) + CELL(1.500 ns) = 2.500 ns; Loc. = LC40; Fanout = 2; REG Node = '74164:inst69\|10'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { 74164:inst69|9 74164:inst69|10 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 896 360 424 976 "10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 60.00 % ) " "Info: Total cell delay = 1.500 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 40.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { 74164:inst69|9 74164:inst69|10 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.500 ns" { 74164:inst69|9 {} 74164:inst69|10 {} } { 0.000ns 1.000ns } { 0.000ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 896 360 424 976 "10" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|9 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { BaudRateMul4 {} BaudRateMul4~out {} COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var {} 74164:inst69|9 {} } { 0.000ns 0.000ns 0.000ns 1.200ns } { 0.000ns 1.000ns 1.300ns 1.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { 74164:inst69|9 74164:inst69|10 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.500 ns" { 74164:inst69|9 {} 74164:inst69|10 {} } { 0.000ns 1.000ns } { 0.000ns 1.500ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}