count4.tan.rpt

FPGA模拟UART

; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; inst3 ; inst4 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------+
; tsu                                                         ;
+-------+--------------+------------+------+-------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To    ; To Clock ;
+-------+--------------+------------+------+-------+----------+
; N/A   ; None         ; 2.000 ns   ; RI   ; inst1 ; CLK      ;
+-------+--------------+------------+------+-------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+-------+------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To   ; From Clock ;
+-------+--------------+------------+-------+------+------------+
; N/A   ; None         ; 3.000 ns   ; inst4 ; Q[3] ; CLK        ;
; N/A   ; None         ; 3.000 ns   ; inst3 ; Q[2] ; CLK        ;
; N/A   ; None         ; 3.000 ns   ; inst2 ; Q[1] ; CLK        ;
; N/A   ; None         ; 3.000 ns   ; inst1 ; Q[0] ; CLK        ;
+-------+--------------+------------+-------+------+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To    ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A           ; None        ; -0.100 ns ; RI   ; inst1 ; CLK      ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Dec 06 13:57:30 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off COUNT4 -c COUNT4
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 227.27 MHz between source register "inst1" and destination register "inst1" (period= 4.4 ns)
    Info: + Longest register to register delay is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
        Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
        Info: Total cell delay = 2.400 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "inst1" (data pin = "RI", clock pin = "CLK") is 2.000 ns
    Info: + Longest pin to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'RI'
        Info: 2: + IC(0.900 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
        Info: Total cell delay = 1.300 ns ( 59.09 % )
        Info: Total interconnect delay = 0.900 ns ( 40.91 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "Q[3]" through register "inst4" is 3.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC5; Fanout = 2; REG Node = 'inst4'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 0.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'inst4'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'Q[3]'
        Info: Total cell delay = 0.800 ns ( 100.00 % )
Info: th for register "inst1" (data pin = "RI", clock pin = "CLK") is -0.100 ns
    Info: + Longest clock path from clock "CLK" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.600 ns
    Info: - Shortest pin to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'RI'
        Info: 2: + IC(0.900 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'
        Info: Total cell delay = 1.300 ns ( 59.09 % )
        Info: Total interconnect delay = 0.900 ns ( 40.91 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sat Dec 06 13:57:31 2008
    Info: Elapsed time: 00:00:01