📄 uarttest.fit.rpt
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+----------------------------+-------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 9.50) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 1.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
+-------------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC9 ; RXD, 74164:inst70|3 ; inst1~2 ;
; A ; LC10 ; COUNT4:inst22|SYNTHESIZED_WIRE_2_synthesized_var, COUNT4:inst22|SYNTHESIZED_WIRE_3_synthesized_var, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin ; COUNT4:inst22|Q_synthesized_var[3] ;
; A ; LC12 ; BaudRateMul4, inst1~2 ; COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ;
; A ; LC11 ; BaudRateMul4, inst1~2, COUNT4:inst25|SYNTHESIZED_WIRE_3_synthesized_var ; 74164:inst69|3, 74164:inst69|4, 74164:inst69|5, 74164:inst69|6, 74164:inst69|7, 74164:inst69|8, 74164:inst69|9, 74164:inst69|10, 74164:inst70|3 ;
; A ; LC14 ; COUNT4:inst22|TFF_inst3_synthesized_var, COUNT4:inst22|SYNTHESIZED_WIRE_2_synthesized_var, COUNT4:inst22|SYNTHESIZED_WIRE_3_synthesized_var, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin ; inst23, inst32~23, inst32~25sexp ;
; A ; LC8 ; 74165:inst9|38, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData5 ; 74165:inst9|65 ;
; A ; LC15 ; COUNT4:inst22|SYNTHESIZED_WIRE_2_synthesized_var, COUNT4:inst22|Q_synthesized_var[3], COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nRESET ; COUNT4:inst22|SYNTHESIZED_WIRE_3_synthesized_var ;
; A ; LC13 ; BaudRateMul4, inst66~5, inst66~6 ; COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var ;
; A ; LC1 ; 74165:inst9|93, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin ; TXD ;
; A ; LC5 ; inst23, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin ; COUNT4:inst22|TFF_inst3_synthesized_var, COUNT4:inst22|Q_synthesized_var[3], COUNT4:inst22|SYNTHESIZED_WIRE_2_synthesized_var ;
; A ; LC3 ; BaudRateMul4, 74164:inst70|3, nRESET ; RI ;
; A ; LC2 ; BaudRateMul4, inst66~5, inst66~6, COUNT4:inst3|SYNTHESIZED_WIRE_3_synthesized_var ; COUNT4:inst22|TFF_inst3_synthesized_var, COUNT4:inst22|Q_synthesized_var[3], inst23, COUNT4:inst22|SYNTHESIZED_WIRE_3_synthesized_var, COUNT4:inst22|SYNTHESIZED_WIRE_2_synthesized_var, 74165:inst7|98, 74165:inst9|38, 74165:inst9|37, 74165:inst9|65, 74165:inst9|70, 74165:inst9|79, 74165:inst9|84, 74165:inst9|93, 74165:inst9|98 ;
; A ; LC6 ; COUNT4:inst22|SYNTHESIZED_WIRE_3_synthesized_var, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin ; COUNT4:inst22|TFF_inst3_synthesized_var, COUNT4:inst22|Q_synthesized_var[3], inst23, inst32~23, inst32~25sexp ;
; A ; LC16 ; COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData7 ; 74165:inst9|38 ;
; A ; LC4 ; COUNT4:inst22|SYNTHESIZED_WIRE_2_synthesized_var, COUNT4:inst22|Q_synthesized_var[3] ; TI ;
; A ; LC7 ; 74165:inst7|98, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData6 ; 74165:inst9|37 ;
; B ; LC29 ; nRecBegin, 74164:inst69|4, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|6, 74377:inst54|34 ;
; B ; LC31 ; nRecBegin, 74164:inst69|5, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|7, 74377:inst54|35 ;
; B ; LC32 ; nRecBegin, 74164:inst69|6, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|8, 74377:inst54|30 ;
; B ; LC18 ; nRecBegin, 74164:inst69|7, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|9, 74377:inst54|31 ;
; B ; LC24 ; nRecBegin, 74164:inst69|8, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|10, 74377:inst54|29 ;
; B ; LC21 ; 74164:inst69|7, 74164:inst70|3, BaudRateMul4 ; RxdD3p ;
; B ; LC25 ; 74164:inst69|8, 74164:inst70|3, BaudRateMul4 ; RxdD2p ;
; B ; LC17 ; 74164:inst69|6, 74164:inst70|3, BaudRateMul4 ; RxdD4p ;
; B ; LC19 ; 74164:inst69|5, 74164:inst70|3, BaudRateMul4 ; RxdD5p ;
; B ; LC30 ; 74165:inst9|37, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData4 ; 74165:inst9|70 ;
; B ; LC22 ; 74165:inst9|65, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData3 ; 74165:inst9|79 ;
; B ; LC23 ; 74165:inst9|70, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData2 ; 74165:inst9|84 ;
; B ; LC26 ; 74165:inst9|79, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData1 ; 74165:inst9|93 ;
; B ; LC28 ; 74165:inst9|84, COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var, nSendBegin, SendData0 ; 74165:inst9|98 ;
; B ; LC20 ; 74164:inst69|4, 74164:inst70|3, BaudRateMul4 ; RxdD6p ;
; C ; LC34 ; nRecBegin, RXD, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|4, 74377:inst54|32 ;
; C ; LC38 ; nRecBegin, 74164:inst69|3, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst69|5, 74377:inst54|33 ;
; C ; LC37 ; nRecBegin, 74164:inst69|9, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; 74164:inst70|3, 74377:inst54|28 ;
; C ; LC48 ; nRecBegin, 74164:inst69|10, 74164:inst70|3, COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var ; inst2, 74164:inst69|3, 74164:inst69|4, 74164:inst69|5, 74164:inst69|6, 74164:inst69|7, 74164:inst69|8, 74164:inst69|9, 74164:inst69|10, 74164:inst70|3, inst19, 74377:inst54|35, 74377:inst54|34, 74377:inst54|33, 74377:inst54|32, 74377:inst54|30, 74377:inst54|31, 74377:inst54|29, 74377:inst54|28 ;
; C ; LC36 ; 74164:inst69|3, 74164:inst70|3, BaudRateMul4 ; RxdD7p ;
; C ; LC33 ; 74164:inst69|9, 74164:inst70|3, BaudRateMul4 ; RxdD1p ;
; C ; LC35 ; 74164:inst69|10, 74164:inst70|3, BaudRateMul4 ; RxdD0p ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+----------------+
; Option ; Setting ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+----------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon Dec 08 12:28:33 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UartTest -c UartTest
Info: Automatically selected device EPM3064ALC44-4 for design UartTest
Info: Fitting design with smaller device may be possible, but smaller device must be specified
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Allocated 143 megabytes of memory during processing
Info: Processing ended: Mon Dec 08 12:28:34 2008
Info: Elapsed time: 00:00:01
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