count4.vhd

FPGA模拟UART

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY COUNT4 IS 
	port
	(
		CLK :  IN  STD_LOGIC;
		nCLR :  IN  STD_LOGIC;
		RI :  IN  STD_LOGIC;
		Q :  OUT  STD_LOGIC_VECTOR(3 downto 0)
	);
END COUNT4;

ARCHITECTURE bdf_type OF COUNT4 IS 

signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	TFF_inst3 :  STD_LOGIC;


BEGIN 
Q(0) <= SYNTHESIZED_WIRE_3;
Q(1) <= SYNTHESIZED_WIRE_2;
Q(2) <= TFF_inst3;



SYNTHESIZED_WIRE_0 <= SYNTHESIZED_WIRE_2 AND SYNTHESIZED_WIRE_3;

process(CLK,nCLR)
variable SYNTHESIZED_WIRE_3_synthesized_var : STD_LOGIC;
begin
if (nCLR = '0') then
	SYNTHESIZED_WIRE_3_synthesized_var := '0';
elsif (rising_edge(CLK)) then
	SYNTHESIZED_WIRE_3_synthesized_var := SYNTHESIZED_WIRE_3_synthesized_var XOR RI;
end if;
	SYNTHESIZED_WIRE_3 <= SYNTHESIZED_WIRE_3_synthesized_var;
end process;

process(CLK,nCLR)
variable SYNTHESIZED_WIRE_2_synthesized_var : STD_LOGIC;
begin
if (nCLR = '0') then
	SYNTHESIZED_WIRE_2_synthesized_var := '0';
elsif (rising_edge(CLK)) then
	SYNTHESIZED_WIRE_2_synthesized_var := SYNTHESIZED_WIRE_2_synthesized_var XOR SYNTHESIZED_WIRE_3;
end if;
	SYNTHESIZED_WIRE_2 <= SYNTHESIZED_WIRE_2_synthesized_var;
end process;

process(CLK,nCLR)
variable TFF_inst3_synthesized_var : STD_LOGIC;
begin
if (nCLR = '0') then
	TFF_inst3_synthesized_var := '0';
elsif (rising_edge(CLK)) then
	TFF_inst3_synthesized_var := TFF_inst3_synthesized_var XOR SYNTHESIZED_WIRE_0;
end if;
	TFF_inst3 <= TFF_inst3_synthesized_var;
end process;

process(CLK,nCLR)
variable Q_synthesized_var : STD_LOGIC_VECTOR(3 to 3);
begin
if (nCLR = '0') then
	Q_synthesized_var(3) := '0';
elsif (rising_edge(CLK)) then
	Q_synthesized_var(3) := Q_synthesized_var(3) XOR SYNTHESIZED_WIRE_1;
end if;
	Q(3) <= Q_synthesized_var(3);
end process;

SYNTHESIZED_WIRE_1 <= TFF_inst3 AND SYNTHESIZED_WIRE_2 AND SYNTHESIZED_WIRE_3;

END;