uarttest.tan.summary

FPGA模拟UART

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.200 ns
From           : RXD
To             : 74164:inst69|3
From Clock     : --
To Clock       : BaudRateMul4
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.300 ns
From           : 74377:inst54|32
To             : RxdD7p
From Clock     : BaudRateMul4
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 8.300 ns
From           : RXD
To             : 74164:inst69|3
From Clock     : --
To Clock       : BaudRateMul4
Failed Paths   : 0

Type           : Clock Setup: 'BaudRateMul4'
Slack          : N/A
Required Time  : None
Actual Time    : 80.65 MHz ( period = 12.400 ns )
From           : 74164:inst69|10
To             : 74377:inst54|28
From Clock     : BaudRateMul4
To Clock       : BaudRateMul4
Failed Paths   : 0

Type           : Clock Hold: 'BaudRateMul4'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : 74164:inst69|9
To             : 74164:inst69|10
From Clock     : BaudRateMul4
To Clock       : BaudRateMul4
Failed Paths   : 16

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 16

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