uarttest.v

FPGA模拟UART

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module UartTest(
	/RESET,
	/CS,
	/WE,
	BaudRateMul4,
	A1,
	/RD,
	RXD,
	TXD,
	TI,
	D0,
	D1,
	D2,
	D3,
	D4,
	D5,
	D6,
	D7
);

input	/RESET;
input	/CS;
input	/WE;
input	BaudRateMul4;
input	A1;
input	/RD;
input	RXD;
output	TXD;
output	TI;
inout	D0;
inout	D1;
inout	D2;
inout	D3;
inout	D4;
inout	D5;
inout	D6;
inout	D7;

wire	/A1;
wire	/RecBegin;
wire	/RI;
wire	/RXD;
wire	/SendBegin;
wire	/TI;
wire	RecBaudRate;
wire	RI;
wire	RxdD0;
wire	RxdD0_;
wire	RxdD1;
wire	RxdD1_;
wire	RxdD2;
wire	RxdD2_;
wire	RxdD3;
wire	RxdD3_;
wire	RxdD4;
wire	RxdD4_;
wire	RxdD5;
wire	RxdD5_;
wire	RxdD6;
wire	RxdD6_;
wire	RxdD7;
wire	RxdD7_;
wire	SendBaudRate;
wire	STOP;
wire	TI_ALTERA_SYNTHESIZED;
wire	TXD_ALTERA_SYNTHESIZED;
reg	DFF_inst2;
wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_61;
wire	SYNTHESIZED_WIRE_62;
wire	SYNTHESIZED_WIRE_13;
wire	SYNTHESIZED_WIRE_63;
wire	SYNTHESIZED_WIRE_15;
wire	SYNTHESIZED_WIRE_16;
reg	DFF_inst23;
wire	SYNTHESIZED_WIRE_17;
wire	SYNTHESIZED_WIRE_18;
wire	SYNTHESIZED_WIRE_19;
wire	SYNTHESIZED_WIRE_20;
wire	SYNTHESIZED_WIRE_21;
wire	SYNTHESIZED_WIRE_22;
wire	SYNTHESIZED_WIRE_23;
wire	SYNTHESIZED_WIRE_24;
wire	SYNTHESIZED_WIRE_26;
wire	SYNTHESIZED_WIRE_27;
wire	SYNTHESIZED_WIRE_28;
wire	SYNTHESIZED_WIRE_64;
wire	SYNTHESIZED_WIRE_65;
wire	SYNTHESIZED_WIRE_34;
wire	SYNTHESIZED_WIRE_66;
wire	SYNTHESIZED_WIRE_42;
wire	SYNTHESIZED_WIRE_43;
wire	SYNTHESIZED_WIRE_44;
wire	SYNTHESIZED_WIRE_45;
wire	SYNTHESIZED_WIRE_46;
wire	SYNTHESIZED_WIRE_47;
wire	SYNTHESIZED_WIRE_48;
wire	SYNTHESIZED_WIRE_50;
wire	SYNTHESIZED_WIRE_51;
wire	SYNTHESIZED_WIRE_52;
wire	SYNTHESIZED_WIRE_53;
wire	SYNTHESIZED_WIRE_54;
wire	SYNTHESIZED_WIRE_55;
wire	SYNTHESIZED_WIRE_56;
wire	SYNTHESIZED_WIRE_57;
wire	SYNTHESIZED_WIRE_58;
wire	SYNTHESIZED_WIRE_59;
wire	SYNTHESIZED_WIRE_60;

assign	SYNTHESIZED_WIRE_61 = 0;
assign	SYNTHESIZED_WIRE_13 = 1;
assign	SYNTHESIZED_WIRE_17 = 1;
assign	SYNTHESIZED_WIRE_19 = 1;
assign	SYNTHESIZED_WIRE_24 = 0;
assign	SYNTHESIZED_WIRE_65 = 0;
assign	SYNTHESIZED_WIRE_56 = 1;



assign	SYNTHESIZED_WIRE_18 = /RESET & DFF_inst2;
assign	SYNTHESIZED_WIRE_53 =  ~SYNTHESIZED_WIRE_0;
assign	SYNTHESIZED_WIRE_63 = A1 | /CS;
assign	SYNTHESIZED_WIRE_52 =  ~SYNTHESIZED_WIRE_1;
assign	SYNTHESIZED_WIRE_58 =  ~SYNTHESIZED_WIRE_2;
assign	SYNTHESIZED_WIRE_59 =  ~SYNTHESIZED_WIRE_3;
assign	SYNTHESIZED_WIRE_55 =  ~SYNTHESIZED_WIRE_4;

\74244 	b2v_inst19(.1A2(SYNTHESIZED_WIRE_61),
.1A4(SYNTHESIZED_WIRE_61),.1A1(SYNTHESIZED_WIRE_61),.1A3(SYNTHESIZED_WIRE_61),.1GN(SYNTHESIZED_WIRE_62),.2A3(RI),.2GN(SYNTHESIZED_WIRE_62),.2A1(SYNTHESIZED_WIRE_61),.2A4(TI_ALTERA_SYNTHESIZED),.2A2(SYNTHESIZED_WIRE_61),.1Y2(D6),.1Y4(D4),.2Y1(D3),.1Y1(D7),.2Y3(D1),.2Y4(D0),.1Y3(D5),.2Y2(D2));

always@(posedge /RXD or negedge /RI)
begin
if (!/RI)
	begin
	DFF_inst2 <= 0;
	end
else
	begin
	DFF_inst2 <= SYNTHESIZED_WIRE_13;
	end
end
assign	SYNTHESIZED_WIRE_62 = /A1 | /RD | /CS;

\74377 	b2v_inst21(.D8(D0),
.D7(D1),.CLK(/WE),.D2(D6),.EN(SYNTHESIZED_WIRE_63),.D1(D7),.D6(D2),.D3(D5),.D4(D4),.D5(D3),.Q8(SYNTHESIZED_WIRE_4),.Q7(SYNTHESIZED_WIRE_3),.Q6(SYNTHESIZED_WIRE_2),.Q5(SYNTHESIZED_WIRE_1),.Q4(SYNTHESIZED_WIRE_0),.Q3(SYNTHESIZED_WIRE_51),.Q1(SYNTHESIZED_WIRE_23),.Q2(SYNTHESIZED_WIRE_26));

\16f-1f_tff 	b2v_inst22(.CI(SYNTHESIZED_WIRE_15),
./CLR(/SendBegin),.CLK(SendBaudRate),.Q1(SYNTHESIZED_WIRE_21),.Q3(SYNTHESIZED_WIRE_22));

always@(posedge SYNTHESIZED_WIRE_16 or negedge /RESET)
begin
if (!/RESET)
	begin
	DFF_inst23 <= 0;
	end
else
	begin
	DFF_inst23 <= TI_ALTERA_SYNTHESIZED;
	end
end
assign	SYNTHESIZED_WIRE_15 =  ~DFF_inst23;

\16f-1f_tff 	b2v_inst25(.CI(SYNTHESIZED_WIRE_17),
./CLR(SYNTHESIZED_WIRE_18),.CLK(BaudRateMul4),.Q1(RecBaudRate));
assign	SYNTHESIZED_WIRE_16 =  ~SendBaudRate;
assign	/TI =  ~TI_ALTERA_SYNTHESIZED;

\16f-1f_tff 	b2v_inst3(.CI(SYNTHESIZED_WIRE_19),
./CLR(SYNTHESIZED_WIRE_20),.CLK(BaudRateMul4),.Q1(SYNTHESIZED_WIRE_27));
assign	TI_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22;
assign	/A1 =  ~A1;

\74244 	b2v_inst40(.1A2(RxdD6_),
.1A4(RxdD4_),.1A1(RxdD7_),.1A3(RxdD5_),.1GN(/RecBegin),.2A3(RxdD1_),.2GN(/RecBegin),.2A1(RxdD3_),.2A4(RxdD0_),.2A2(RxdD2_),.1Y2(D6),.1Y4(D4),.2Y1(D3),.1Y1(D7),.2Y3(D1),.2Y4(D0),.1Y3(D5),.2Y2(D2));
assign	/RecBegin = A1 | /RD | /CS;
assign	/RXD =  ~TXD_ALTERA_SYNTHESIZED;
assign	SYNTHESIZED_WIRE_34 =  ~SYNTHESIZED_WIRE_23;

\74377 	b2v_inst54(.D8(RxdD0),
.D7(RxdD1),.CLK(/RI),.D2(RxdD6),.EN(SYNTHESIZED_WIRE_24),.D1(RxdD7),.D6(RxdD2),.D3(RxdD5),.D4(RxdD4),.D5(RxdD3),.Q8(RxdD0_),.Q7(RxdD1_),.Q6(RxdD2_),.Q5(RxdD3_),.Q4(RxdD4_),.Q3(RxdD5_),.Q1(RxdD7_),.Q2(RxdD6_));
assign	/SendBegin = SYNTHESIZED_WIRE_63 | /WE;
assign	SYNTHESIZED_WIRE_57 =  ~SYNTHESIZED_WIRE_26;
assign	SendBaudRate =  ~SYNTHESIZED_WIRE_27;
assign	SYNTHESIZED_WIRE_28 = /SendBegin | /RESET;
assign	SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_28 & /TI;

\74164 	b2v_inst69(.CLRN(/RecBegin),
.CLK(SYNTHESIZED_WIRE_64),.B(/RXD),.A(/RXD),.QD(SYNTHESIZED_WIRE_45),.QC(SYNTHESIZED_WIRE_44),.QA(SYNTHESIZED_WIRE_42),.QF(SYNTHESIZED_WIRE_47),.QH(SYNTHESIZED_WIRE_66),.QG(SYNTHESIZED_WIRE_48),.QE(SYNTHESIZED_WIRE_46),.QB(SYNTHESIZED_WIRE_43));

\74165 	b2v_inst7(.D(SYNTHESIZED_WIRE_65),
.C(SYNTHESIZED_WIRE_65),.B(SYNTHESIZED_WIRE_65),.G(SYNTHESIZED_WIRE_65),.H(SYNTHESIZED_WIRE_34),.A(SYNTHESIZED_WIRE_65),.E(SYNTHESIZED_WIRE_65),.F(SYNTHESIZED_WIRE_65),.CLK(SendBaudRate),.STLD(/WE),.SER(SYNTHESIZED_WIRE_65),.QH(SYNTHESIZED_WIRE_60));

\74164 	b2v_inst70(.CLRN(/RecBegin),
.CLK(SYNTHESIZED_WIRE_64),.B(SYNTHESIZED_WIRE_66),.A(SYNTHESIZED_WIRE_66),.QA(SYNTHESIZED_WIRE_50),.QB(RI));
assign	RxdD7 =  ~SYNTHESIZED_WIRE_43;
assign	RxdD6 =  ~SYNTHESIZED_WIRE_44;
assign	RxdD5 =  ~SYNTHESIZED_WIRE_45;
assign	RxdD4 =  ~SYNTHESIZED_WIRE_46;
assign	RxdD3 =  ~SYNTHESIZED_WIRE_47;
assign	RxdD2 =  ~SYNTHESIZED_WIRE_48;
assign	RxdD1 =  ~SYNTHESIZED_WIRE_66;
assign	RxdD0 =  ~SYNTHESIZED_WIRE_50;
assign	SYNTHESIZED_WIRE_54 =  ~SYNTHESIZED_WIRE_51;
assign	/RI =  ~RI;
assign	SYNTHESIZED_WIRE_64 = RecBaudRate & /RI;

\74165 	b2v_inst9(.D(SYNTHESIZED_WIRE_52),
.C(SYNTHESIZED_WIRE_53),.B(SYNTHESIZED_WIRE_54),.G(SYNTHESIZED_WIRE_55),.H(SYNTHESIZED_WIRE_56),.A(SYNTHESIZED_WIRE_57),.E(SYNTHESIZED_WIRE_58),.F(SYNTHESIZED_WIRE_59),.CLK(SendBaudRate),.STLD(/WE),.SER(SYNTHESIZED_WIRE_60),.QHN(TXD_ALTERA_SYNTHESIZED));
assign	TXD = TXD_ALTERA_SYNTHESIZED;
assign	TI = TI_ALTERA_SYNTHESIZED;


endmodule