uarttest.map.rpt

FPGA模拟UART

; I/O pins             ; 24                   ;
; Shareable expanders  ; 4                    ;
; Maximum fan-out node ; 74164:inst70|3       ;
; Maximum fan-out      ; 19                   ;
; Total fan-out        ; 151                  ;
; Average fan-out      ; 2.29                 ;
+----------------------+----------------------+


+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                     ;
+----------------------------+------------+------+-------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name     ; Library Name ;
+----------------------------+------------+------+-------------------------+--------------+
; |UartTest                  ; 38         ; 24   ; |UartTest               ; work         ;
;    |74164:inst69|          ; 8          ; 0    ; |UartTest|74164:inst69  ; work         ;
;    |74164:inst70|          ; 1          ; 0    ; |UartTest|74164:inst70  ; work         ;
;    |74165:inst7|           ; 1          ; 0    ; |UartTest|74165:inst7   ; work         ;
;    |74165:inst9|           ; 8          ; 0    ; |UartTest|74165:inst9   ; work         ;
;    |74377:inst54|          ; 8          ; 0    ; |UartTest|74377:inst54  ; work         ;
;    |COUNT4:inst22|         ; 4          ; 0    ; |UartTest|COUNT4:inst22 ; work         ;
;    |COUNT4:inst25|         ; 2          ; 0    ; |UartTest|COUNT4:inst25 ; work         ;
;    |COUNT4:inst3|          ; 2          ; 0    ; |UartTest|COUNT4:inst3  ; work         ;
+----------------------------+------------+------+-------------------------+--------------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; 74165:inst7|38                        ; Stuck at GND due to stuck port data_in ;
; 74165:inst7|37                        ; Stuck at GND due to stuck port data_in ;
; 74165:inst7|65                        ; Stuck at GND due to stuck port data_in ;
; 74165:inst7|70                        ; Stuck at GND due to stuck port data_in ;
; 74165:inst7|79                        ; Stuck at GND due to stuck port data_in ;
; 74165:inst7|84                        ; Stuck at GND due to stuck port data_in ;
; 74165:inst7|93                        ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 7 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                  ;
+----------------+---------------------------+---------------------------------------------------------------------------------+
; Register name  ; Reason for Removal        ; Registers Removed due to This Register                                          ;
+----------------+---------------------------+---------------------------------------------------------------------------------+
; 74165:inst7|38 ; Stuck at GND              ; 74165:inst7|37, 74165:inst7|65, 74165:inst7|70, 74165:inst7|79, 74165:inst7|84, ;
;                ; due to stuck port data_in ; 74165:inst7|93                                                                  ;
+----------------+---------------------------+---------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon Dec 08 12:28:30 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UartTest -c UartTest
Info: Found 1 design units, including 1 entities, in source file UartTest.bdf
    Info: Found entity 1: UartTest
Info: Elaborating entity "UartTest" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst5" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst71" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst73" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst75" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst77" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst8" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst13" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst15" overlaps another block or symbol
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/others/maxplus2/74165.bdf
    Info: Found entity 1: 74165
Info: Elaborating entity "74165" for hierarchy "74165:inst9"
Warning: Processing legacy GDF or BDF entity "74165" with Max+Plus II bus and instance naming rules
Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s).
Info: Elaborated megafunction instantiation "74165:inst9"
Warning: Using design file COUNT4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: COUNT4-bdf_type
    Info: Found entity 1: COUNT4
Warning (12300): Found the following files while searching for definition of entity "COUNT4", but did not use these files because already using a different file containing the entity definition
    Warning: File: COUNT4.bdf
Info: Elaborating entity "COUNT4" for hierarchy "COUNT4:inst3"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf
    Info: Found entity 1: 74164
Info: Elaborating entity "74164" for hierarchy "74164:inst70"
Warning: Processing legacy GDF or BDF entity "74164" with Max+Plus II bus and instance naming rules
Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s).
Info: Elaborated megafunction instantiation "74164:inst70"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/others/maxplus2/74377.bdf
    Info: Found entity 1: 74377
Info: Elaborating entity "74377" for hierarchy "74377:inst54"
Warning: Processing legacy GDF or BDF entity "74377" with Max+Plus II bus and instance naming rules
Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s).
Info: Elaborated megafunction instantiation "74377:inst54"
Warning (14130): Reduced register "74165:inst7|38" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "74165:inst7|37" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "74165:inst7|65" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "74165:inst7|70" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "74165:inst7|79" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "74165:inst7|84" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "74165:inst7|93" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "BaudRateMul4" to global clock signal
    Info: Promoted clock signal driven by pin "RXD" to global clock signal
    Info: Promoted clear signal driven by pin "nRecBegin" to global clear signal
Info: Implemented 66 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 11 output pins
    Info: Implemented 38 macrocells
    Info: Implemented 4 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Mon Dec 08 12:28:32 2008
    Info: Elapsed time: 00:00:02