74165_5.vhd

FPGA模拟UART

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
LIBRARY work;

ENTITY 74165_5 IS 
PORT 
( 
	D	:	IN	 STD_LOGIC;
	C	:	IN	 STD_LOGIC;
	B	:	IN	 STD_LOGIC;
	G	:	IN	 STD_LOGIC;
	H	:	IN	 STD_LOGIC;
	A	:	IN	 STD_LOGIC;
	E	:	IN	 STD_LOGIC;
	F	:	IN	 STD_LOGIC;
	CLK	:	IN	 STD_LOGIC;
	STLD	:	IN	 STD_LOGIC;
	SER	:	IN	 STD_LOGIC;
	QH	:	OUT	 STD_LOGIC
); 
END 74165_5;

ARCHITECTURE bdf_type OF 74165_5 IS 
BEGIN 

-- instantiate macrofunction 

b2v_inst7 : 74165
PORT MAP(D => D,
		 C => C,
		 B => B,
		 G => G,
		 H => H,
		 A => A,
		 E => E,
		 F => F,
		 CLK => CLK,
		 STLD => STLD,
		 SER => SER,
		 QH => QH);

END;