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📄 uarttest.inc

📁 FPGA模拟UART
💻 INC
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 7.2 (Build Build 151 09/26/2007)
-- Created on Mon Dec 08 12:30:26 2008

FUNCTION UartTest (BaudRateMul4, RXD, SendData0, SendData1, SendData2, SendData3, SendData4, SendData5, SendData6, SendData7, nRESET, nSendBegin, nRecBegin)
	RETURNS (TXD, TI, RI, RxdD7p, RxdD6p, RxdD5p, RxdD4p, RxdD3p, RxdD2p, RxdD1p, RxdD0p);

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