uarttest.vhd

FPGA模拟UART

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY UartTest IS 
	port
	(
		BaudRateMul4 :  IN  STD_LOGIC;
		RXD :  IN  STD_LOGIC;
		SendData0 :  IN  STD_LOGIC;
		SendData1 :  IN  STD_LOGIC;
		SendData2 :  IN  STD_LOGIC;
		SendData3 :  IN  STD_LOGIC;
		SendData4 :  IN  STD_LOGIC;
		SendData5 :  IN  STD_LOGIC;
		SendData6 :  IN  STD_LOGIC;
		SendData7 :  IN  STD_LOGIC;
		nRESET :  IN  STD_LOGIC;
		nSendBegin :  IN  STD_LOGIC;
		nRecBegin :  IN  STD_LOGIC;
		TXD :  OUT  STD_LOGIC;
		TI :  OUT  STD_LOGIC;
		RI :  OUT  STD_LOGIC;
		RxdD7p :  OUT  STD_LOGIC;
		RxdD6p :  OUT  STD_LOGIC;
		RxdD5p :  OUT  STD_LOGIC;
		RxdD4p :  OUT  STD_LOGIC;
		RxdD3p :  OUT  STD_LOGIC;
		RxdD2p :  OUT  STD_LOGIC;
		RxdD1p :  OUT  STD_LOGIC;
		RxdD0p :  OUT  STD_LOGIC
	);
END UartTest;

ARCHITECTURE bdf_type OF UartTest IS 

attribute black_box : boolean;
attribute noopt : boolean;

component \74164_1\
	PORT(CLRN : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 QD : OUT STD_LOGIC;
		 QC : OUT STD_LOGIC;
		 QA : OUT STD_LOGIC;
		 QF : OUT STD_LOGIC;
		 QH : OUT STD_LOGIC;
		 QG : OUT STD_LOGIC;
		 QE : OUT STD_LOGIC;
		 QB : OUT STD_LOGIC);
end component;
attribute black_box of \74164_1\: component is true;
attribute noopt of \74164_1\: component is true;

component \74164_3\
	PORT(CLRN : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 QA : OUT STD_LOGIC);
end component;
attribute black_box of \74164_3\: component is true;
attribute noopt of \74164_3\: component is true;

component \74165_2\
	PORT(D : IN STD_LOGIC;
		 C : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 G : IN STD_LOGIC;
		 H : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 E : IN STD_LOGIC;
		 F : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 STLD : IN STD_LOGIC;
		 SER : IN STD_LOGIC;
		 QH : OUT STD_LOGIC);
end component;
attribute black_box of \74165_2\: component is true;
attribute noopt of \74165_2\: component is true;

component \74165_4\
	PORT(D : IN STD_LOGIC;
		 C : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 G : IN STD_LOGIC;
		 H : IN STD_LOGIC;
		 A : IN STD_LOGIC;
		 E : IN STD_LOGIC;
		 F : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 STLD : IN STD_LOGIC;
		 SER : IN STD_LOGIC;
		 QHN : OUT STD_LOGIC);
end component;
attribute black_box of \74165_4\: component is true;
attribute noopt of \74165_4\: component is true;

component \74377_0\
	PORT(D8 : IN STD_LOGIC;
		 D7 : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 D2 : IN STD_LOGIC;
		 EN : IN STD_LOGIC;
		 D1 : IN STD_LOGIC;
		 D6 : IN STD_LOGIC;
		 D3 : IN STD_LOGIC;
		 D4 : IN STD_LOGIC;
		 D5 : IN STD_LOGIC;
		 Q8 : OUT STD_LOGIC;
		 Q7 : OUT STD_LOGIC;
		 Q6 : OUT STD_LOGIC;
		 Q5 : OUT STD_LOGIC;
		 Q4 : OUT STD_LOGIC;
		 Q3 : OUT STD_LOGIC;
		 Q1 : OUT STD_LOGIC;
		 Q2 : OUT STD_LOGIC);
end component;
attribute black_box of \74377_0\: component is true;
attribute noopt of \74377_0\: component is true;

component count4
	PORT(RI : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 nCLR : IN STD_LOGIC;
		 Q : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

signal	nBaudRateMul4 :  STD_LOGIC;
signal	nRI :  STD_LOGIC;
signal	nRXD :  STD_LOGIC;
signal	nTI :  STD_LOGIC;
signal	RecBaudRate :  STD_LOGIC;
signal	RI_0 :  STD_LOGIC;
signal	RxdD0 :  STD_LOGIC;
signal	RxdD1 :  STD_LOGIC;
signal	RxdD2 :  STD_LOGIC;
signal	RxdD3 :  STD_LOGIC;
signal	RxdD4 :  STD_LOGIC;
signal	RxdD5 :  STD_LOGIC;
signal	RxdD6 :  STD_LOGIC;
signal	RxdD7 :  STD_LOGIC;
signal	SendBaudRate :  STD_LOGIC;
signal	TI_ALTERA_SYNTHESIZED :  STD_LOGIC;
signal	DFF_inst2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	DFF_inst23 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_43 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_44 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_45 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_46 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_26 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_27 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_28 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_29 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_30 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_31 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_32 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_34 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_35 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_36 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_37 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_38 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_39 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_40 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_41 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_42 :  STD_LOGIC;

signal	GDFX_TEMP_SIGNAL_0 :  STD_LOGIC_VECTOR(3 downto 0);

BEGIN 
SYNTHESIZED_WIRE_0 <= '1';
SYNTHESIZED_WIRE_3 <= '1';
SYNTHESIZED_WIRE_5 <= '1';
SYNTHESIZED_WIRE_10 <= '0';
SYNTHESIZED_WIRE_45 <= '0';
SYNTHESIZED_WIRE_38 <= '1';

RecBaudRate <= GDFX_TEMP_SIGNAL_0(3);



SYNTHESIZED_WIRE_9 <= nBaudRateMul4 AND RI_0;

SYNTHESIZED_WIRE_4 <= nRESET AND DFF_inst2;

SYNTHESIZED_WIRE_35 <= NOT(SendData4);


SYNTHESIZED_WIRE_34 <= NOT(SendData3);


SYNTHESIZED_WIRE_40 <= NOT(SendData2);


SYNTHESIZED_WIRE_41 <= NOT(SendData1);


SYNTHESIZED_WIRE_37 <= NOT(SendData0);


process(BaudRateMul4,nRESET)
begin
if (nRESET = '0') then
	RI <= '0';
elsif (rising_edge(BaudRateMul4)) then
	RI <= RI_0;
end if;
end process;

process(nRXD,nRI)
begin
if (nRI = '0') then
	DFF_inst2 <= '0';
elsif (rising_edge(nRXD)) then
	DFF_inst2 <= SYNTHESIZED_WIRE_0;
end if;
end process;

nBaudRateMul4 <= NOT(BaudRateMul4);


b2v_inst22 : count4
PORT MAP(RI => SYNTHESIZED_WIRE_1,
		 CLK => SendBaudRate,
		 nCLR => nSendBegin,
		 Q => SYNTHESIZED_WIRE_43);

process(SYNTHESIZED_WIRE_2,nRESET)
begin
if (nRESET = '0') then
	DFF_inst23 <= '0';
elsif (rising_edge(SYNTHESIZED_WIRE_2)) then
	DFF_inst23 <= TI_ALTERA_SYNTHESIZED;
end if;
end process;

SYNTHESIZED_WIRE_1 <= NOT(DFF_inst23);


b2v_inst25 : count4
PORT MAP(RI => SYNTHESIZED_WIRE_3,
		 CLK => BaudRateMul4,
		 nCLR => SYNTHESIZED_WIRE_4,
		 Q => GDFX_TEMP_SIGNAL_0);

SYNTHESIZED_WIRE_2 <= NOT(SendBaudRate);


nTI <= NOT(TI_ALTERA_SYNTHESIZED);


b2v_inst3 : count4
PORT MAP(RI => SYNTHESIZED_WIRE_5,
		 CLK => BaudRateMul4,
		 nCLR => SYNTHESIZED_WIRE_6,
		 Q => SYNTHESIZED_WIRE_11);

TI_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_43 AND SYNTHESIZED_WIRE_43;

nRXD <= NOT(RXD);


SYNTHESIZED_WIRE_18 <= NOT(SendData7);


b2v_inst54 : 74377_0
PORT MAP(D8 => RxdD0,
		 D7 => RxdD1,
		 CLK => SYNTHESIZED_WIRE_9,
		 D2 => RxdD6,
		 EN => SYNTHESIZED_WIRE_10,
		 D1 => RxdD7,
		 D6 => RxdD2,
		 D3 => RxdD5,
		 D4 => RxdD4,
		 D5 => RxdD3,
		 Q8 => RxdD0p,
		 Q7 => RxdD1p,
		 Q6 => RxdD2p,
		 Q5 => RxdD3p,
		 Q4 => RxdD4p,
		 Q3 => RxdD5p,
		 Q1 => RxdD7p,
		 Q2 => RxdD6p);

SYNTHESIZED_WIRE_39 <= NOT(SendData6);


SendBaudRate <= NOT(SYNTHESIZED_WIRE_11);


SYNTHESIZED_WIRE_12 <= nSendBegin OR nRESET;

SYNTHESIZED_WIRE_6 <= SYNTHESIZED_WIRE_12 AND nTI;

b2v_inst69 : 74164_1
PORT MAP(CLRN => nRecBegin,
		 CLK => SYNTHESIZED_WIRE_44,
		 B => nRXD,
		 A => nRXD,
		 QD => SYNTHESIZED_WIRE_29,
		 QC => SYNTHESIZED_WIRE_28,
		 QA => SYNTHESIZED_WIRE_26,
		 QF => SYNTHESIZED_WIRE_31,
		 QH => SYNTHESIZED_WIRE_46,
		 QG => SYNTHESIZED_WIRE_32,
		 QE => SYNTHESIZED_WIRE_30,
		 QB => SYNTHESIZED_WIRE_27);

b2v_inst7 : 74165_2
PORT MAP(D => SYNTHESIZED_WIRE_45,
		 C => SYNTHESIZED_WIRE_45,
		 B => SYNTHESIZED_WIRE_45,
		 G => SYNTHESIZED_WIRE_45,
		 H => SYNTHESIZED_WIRE_18,
		 A => SYNTHESIZED_WIRE_45,
		 E => SYNTHESIZED_WIRE_45,
		 F => SYNTHESIZED_WIRE_45,
		 CLK => SendBaudRate,
		 STLD => nSendBegin,
		 SER => SYNTHESIZED_WIRE_45,
		 QH => SYNTHESIZED_WIRE_42);

b2v_inst70 : 74164_3
PORT MAP(CLRN => nRecBegin,
		 CLK => SYNTHESIZED_WIRE_44,
		 B => SYNTHESIZED_WIRE_46,
		 A => SYNTHESIZED_WIRE_46,
		 QA => RI_0);

RxdD7 <= NOT(SYNTHESIZED_WIRE_26);


RxdD6 <= NOT(SYNTHESIZED_WIRE_27);


RxdD5 <= NOT(SYNTHESIZED_WIRE_28);


RxdD4 <= NOT(SYNTHESIZED_WIRE_29);


RxdD3 <= NOT(SYNTHESIZED_WIRE_30);


RxdD2 <= NOT(SYNTHESIZED_WIRE_31);


RxdD1 <= NOT(SYNTHESIZED_WIRE_32);


RxdD0 <= NOT(SYNTHESIZED_WIRE_46);


nRI <= NOT(RI_0);


SYNTHESIZED_WIRE_36 <= NOT(SendData5);


SYNTHESIZED_WIRE_44 <= RecBaudRate AND nRI;

b2v_inst9 : 74165_4
PORT MAP(D => SYNTHESIZED_WIRE_34,
		 C => SYNTHESIZED_WIRE_35,
		 B => SYNTHESIZED_WIRE_36,
		 G => SYNTHESIZED_WIRE_37,
		 H => SYNTHESIZED_WIRE_38,
		 A => SYNTHESIZED_WIRE_39,
		 E => SYNTHESIZED_WIRE_40,
		 F => SYNTHESIZED_WIRE_41,
		 CLK => SendBaudRate,
		 STLD => nSendBegin,
		 SER => SYNTHESIZED_WIRE_42,
		 QHN => TXD);
TI <= TI_ALTERA_SYNTHESIZED;

RecBaudRate <= GDFX_TEMP_SIGNAL_0(1);
END;