io.h

ucos在所有cpu下的移植范例

/*	IO DEFINITIONS FOR MC68HC12
 *	Copyright (c) 1996 by COSMIC Software
 */
#define _BASE	0
#define _IO(x)	@_BASE+x
#if _BASE == 0
#define _PORT	@dir
#else
#define _PORT
#endif

_PORT volatile	char PORTA  _IO(0x00);	/* port A */
_PORT volatile	char PORTB  _IO(0x01);	/* port B */
_PORT		char DDRA   _IO(0x02);	/* data direction port A */
_PORT		char DDRB   _IO(0x03);	/* data direction port B */
_PORT volatile	char PORTC  _IO(0x04);	/* port C */
_PORT volatile	char PORTD  _IO(0x05);	/* port D */
_PORT		char DDRC   _IO(0x06);	/* data direction port C */
_PORT		char DDRD   _IO(0x07);	/* data direction port D */
_PORT volatile	char PORTE  _IO(0x08);	/* port E */
_PORT		char DDRE   _IO(0x09);	/* data direction port E */
_PORT		char PEAR   _IO(0x0a);	/* port E assignment register */
_PORT		char MODE   _IO(0x0b);	/* mode register */
_PORT		char PUCR   _IO(0x0c);	/* pull-up control register */
_PORT		char RDRIV  _IO(0x0d);	/* reduced drive of I/O lines */

_PORT		char INITRM _IO(0x10);	/* RAM mapping register */
_PORT		char INITRG _IO(0x11);	/* IO mapping register */
_PORT		char INITEE _IO(0x12);	/* EEPROM mapping register */
_PORT		char MISC   _IO(0x13);	/* mapping control register */
_PORT		char RTICTL _IO(0x14);	/* real time interrupt control */
_PORT volatile	char RTIFLG _IO(0x15);	/* real time interrupt flag */
_PORT		char COPCTL _IO(0x16);	/* COP control register */
_PORT volatile	char COPRST _IO(0x17);	/* COP arm/reset */
_PORT		char ITST0  _IO(0x18);	/* interrupt test 0 */
_PORT		char ITST1  _IO(0x19);	/* interrupt test 1 */
_PORT		char ITST2  _IO(0x1a);	/* interrupt test 2 */
_PORT		char ITST3  _IO(0x1b);	/* interrupt test 3 */
_PORT		char INTCR  _IO(0x1e);	/* interrupt control */
_PORT		char HPRIO  _IO(0x1f);	/* highest priority */

_PORT		char KWIED  _IO(0x20);	/* Wake up interrupt enable D */
_PORT volatile	char KWIFD  _IO(0x21);	/* Wake up flag register D */
_PORT volatile	char PORTH  _IO(0x24);	/* port H */
_PORT		char DDRH   _IO(0x25);	/* data direction port H */
_PORT		char KWIEH  _IO(0x26);	/* Wake up interrupt enable H */
_PORT volatile	char KWIFH  _IO(0x27);	/* Wake up flag register H */
_PORT volatile	char PORTJ  _IO(0x28);	/* port J */
_PORT		char DDRJ   _IO(0x29);	/* data direction port J */
_PORT		char KWIEJ  _IO(0x2a);	/* Wake up interrupt enable J */
_PORT volatile	char KWIFJ  _IO(0x2b);	/* Wake up flag register J */
_PORT		char KPOLJ  _IO(0x2c);	/* Wake up polarity J */
_PORT		char PUPSJ  _IO(0x2d);	/* pull-up select J */
_PORT		char PUPEJ  _IO(0x2e);	/* pull-up enable J */

_PORT volatile	char PORTF  _IO(0x30);	/* port F */
_PORT volatile	char PORTG  _IO(0x31);	/* port G */
_PORT		char DDRF   _IO(0x32);	/* data direction port F */
_PORT		char DDRG   _IO(0x33);	/* data direction port G */
_PORT		char DPAGE  _IO(0x34);	/* data page register */
_PORT		char PPAGE  _IO(0x35);	/* program page register */
_PORT		char EPAGE  _IO(0x36);	/* extra page register */
_PORT		char WINDEF _IO(0x37);	/* window definition */
_PORT		char MXAR   _IO(0x38);	/* memory expansion assignment */
_PORT		char CSCTL0 _IO(0x3c);	/* chip select control 0 */
_PORT		char CSCTL1 _IO(0x3d);	/* chip select control 1 */
_PORT		char CSSTR0 _IO(0x3e);	/* chip select stretch 0 */
_PORT		char CSSTR1 _IO(0x3f);	/* chip select stretch 1 */

_PORT		int  LDV    _IO(0x40);	/* pll loop divider */
_PORT		int  RDV    _IO(0x42);	/* pll reference divider */
_PORT		char CLKCTL _IO(0x47);	/* clock control register */

_PORT         	char ATDCTL0 _IO(0x60);	/* A/D control register 0 */
_PORT         	char ATDCTL1 _IO(0x61);	/* A/D control register 1 */
_PORT         	char ATDCTL2 _IO(0x62);	/* A/D control register 2 */
_PORT         	char ATDCTL3 _IO(0x63);	/* A/D control register 3 */
_PORT         	char ATDCTL4 _IO(0x64);	/* A/D control register 4 */
_PORT         	char ATDCTL5 _IO(0x65);	/* A/D control register 5 */
_PORT         	int  ATDSTAT _IO(0x66);	/* A/D status register */
_PORT         	int  ATDTEST _IO(0x68);	/* A/D test register */
_PORT volatile	char PORTAD  _IO(0x6f);	/* port AD data input register */
_PORT volatile	char ADR0H   _IO(0x70);	/* A/D result 0 */
_PORT volatile	char ADR1H   _IO(0x72);	/* A/D result 1 */
_PORT volatile	char ADR2H   _IO(0x74);	/* A/D result 2 */
_PORT volatile	char ADR3H   _IO(0x76);	/* A/D result 3 */
_PORT volatile	char ADR4H   _IO(0x78);	/* A/D result 4 */
_PORT volatile	char ADR5H   _IO(0x7a);	/* A/D result 5 */
_PORT volatile	char ADR6H   _IO(0x7c);	/* A/D result 6 */
_PORT volatile	char ADR7H   _IO(0x7e);	/* A/D result 7 */

_PORT		char TIOS   _IO(0x80);	/* time select */
_PORT		char CFORC  _IO(0x81);	/* compare force */
_PORT		char OC7M   _IO(0x82);	/* oc7 mask */
_PORT		char OC7D   _IO(0x83);	/* oc7 data */
_PORT volatile	int  TCNT   _IO(0x84);	/* timer counter */
_PORT		char TSCR   _IO(0x86);	/* timer system control */
_PORT		char TQCR   _IO(0x87);	/* timer queue control */
_PORT		char TCTL1  _IO(0x88);	/* timer control 1 */
_PORT		char TCTL2  _IO(0x89);	/* timer control 2 */
_PORT		char TCTL3  _IO(0x8a);	/* timer control 3 */
_PORT		char TCTL4  _IO(0x8b);	/* timer control 4 */
_PORT		char TMSK1  _IO(0x8c);	/* timer interrupt mask 1 */
_PORT		char TMSK2  _IO(0x8d);	/* timer interrupt mask 2 */
_PORT volatile	char TFLG1  _IO(0x8e);	/* timer interrupt flag 1 */
_PORT volatile	char TFLG2  _IO(0x8f);	/* timer interrupt flag 2 */
_PORT volatile	int  TC0    _IO(0x90);	/* timer capture/compare 0 */
_PORT volatile	int  TC1    _IO(0x92);	/* timer capture/compare 1 */
_PORT volatile	int  TC2    _IO(0x94);	/* timer capture/compare 2 */
_PORT volatile	int  TC3    _IO(0x96);	/* timer capture/compare 3 */
_PORT volatile	int  TC4    _IO(0x98);	/* timer capture/compare 4 */
_PORT volatile	int  TC5    _IO(0x9a);	/* timer capture/compare 5 */
_PORT volatile	int  TC6    _IO(0x9c);	/* timer capture/compare 6 */
_PORT volatile	int  TC7    _IO(0x9e);	/* timer capture/compare 7 */
_PORT		char PACTL  _IO(0xa0);	/* pulse accumulator control */
_PORT		char PAFLG  _IO(0xa1);	/* pulse accumulator flag */
_PORT		int  PACNT  _IO(0xa2);	/* pulse accumulator count */
_PORT		char TIMTST _IO(0xad);	/* timer test register */
_PORT volatile	char PORTT  _IO(0xae);	/* timer port data */
_PORT		char DDRT   _IO(0xaf);	/* timer data direction */

_PORT		char SC0BDH _IO(0xc0);	/* SCI 0 baud rate high */
_PORT		char SC0BDL _IO(0xc1);	/* SCI 0 baud rate low */
_PORT		char SC0CR1 _IO(0xc2);	/* SCI 0 control register 1 */
_PORT		char SC0CR2 _IO(0xc3);	/* SCI 0 control register 2 */
_PORT volatile	char SC0SR1 _IO(0xc4);	/* SCI 0 status register 1 */
_PORT volatile	char SC0SR2 _IO(0xc5);	/* SCI 0 status register 2 */
_PORT volatile	char SC0DRH _IO(0xc6);	/* SCI 0 data register high */
_PORT volatile	char SC0DRL _IO(0xc7);	/* SCI 0 data register low */
_PORT		char SC1BDH _IO(0xc8);	/* SCI 1 baud rate high */
_PORT		char SC1BDL _IO(0xc9);	/* SCI 1 baud rate low */
_PORT		char SC1CR1 _IO(0xca);	/* SCI 1 control register 1 */
_PORT		char SC1CR2 _IO(0xcb);	/* SCI 1 control register 2 */
_PORT volatile	char SC1SR1 _IO(0xcc);	/* SCI 1 status register 1 */
_PORT volatile	char SC1SR2 _IO(0xcd);	/* SCI 1 status register 2 */
_PORT volatile	char SC1DRH _IO(0xce);	/* SCI 1 data register high */
_PORT volatile	char SC1DRL _IO(0xcf);	/* SCI 1 data register low */

_PORT		char SP0CR1 _IO(0xd0);	/* SPI control register 1 */
_PORT		char SP0CR2 _IO(0xd1);	/* SPI control register 2 */
_PORT		char SP0BR  _IO(0xd2);	/* SPI baud rate register */
_PORT volatile	char SP0SR  _IO(0xd3);	/* SPI status register */
_PORT volatile	char SP0DR  _IO(0xd5);	/* SPI data register */
_PORT volatile	char PORTS  _IO(0xd6);	/* port S data register */
_PORT		char DDRS   _IO(0xd7);	/* port S data direction */

_PORT         	char EEMCR  _IO(0xf0);	/* eeprom module configuration */
_PORT         	char EEPROT _IO(0xf1);	/* eeprom block protect */
_PORT         	char EETST  _IO(0xf2);	/* eeprom test register */
_PORT volatile	char EEPROG _IO(0xf3);	/* eeprom control register */