📄 stb0899_dvbs2util.c
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csmParams.AgcGain = 6;
csmParams.AgcShift = 0;
csmParams.FeLoopShift = 0;
csmParams.PhaseDiffThreshold = 0x80;
if( ((MasterClock / SymbolRate) <= 4) && (ModCode <= 11) && (Pilots == 1))
{
switch (ModCode)
{
case FE_QPSK_12:
csmParams.GammaAcq = 25;
csmParams.GammaRhoAcq = 2700;
csmParams.GammaTrack = 12;
csmParams.GammaRhoTrack = 180;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_35:
csmParams.GammaAcq = 38;
csmParams.GammaRhoAcq = 7182;
csmParams.GammaTrack = 14;
csmParams.GammaRhoTrack = 308;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_23:
csmParams.GammaAcq = 42;
csmParams.GammaRhoAcq = 9408;
csmParams.GammaTrack = 17;
csmParams.GammaRhoTrack = 476;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_34:
csmParams.GammaAcq = 53;
csmParams.GammaRhoAcq = 16642;
csmParams.GammaTrack = 19;
csmParams.GammaRhoTrack = 646;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_45:
csmParams.GammaAcq = 53;
csmParams.GammaRhoAcq = 17119;
csmParams.GammaTrack = 22;
csmParams.GammaRhoTrack = 880;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_56:
csmParams.GammaAcq = 55;
csmParams.GammaRhoAcq = 19250;
csmParams.GammaTrack = 23;
csmParams.GammaRhoTrack = 989;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_89:
csmParams.GammaAcq = 60;
csmParams.GammaRhoAcq = 24240;
csmParams.GammaTrack = 24;
csmParams.GammaRhoTrack = 1176;
csmParams.LockCountThreshold = 8;
break;
case FE_QPSK_910:
csmParams.GammaAcq = 66;
csmParams.GammaRhoAcq = 29634;
csmParams.GammaTrack = 24;
csmParams.GammaRhoTrack = 1176;
csmParams.LockCountThreshold = 8;
break;
default:
csmParams.GammaAcq = 66;
csmParams.GammaRhoAcq = 29634;
csmParams.GammaTrack = 24;
csmParams.GammaRhoTrack = 1176;
csmParams.LockCountThreshold = 8;
break;
}
FE_DVBS2_ManualConfigCSM(hChip, csmParams);
}
}
/* read csm lock */
static int
FE_DVBS2_GetCSMLock(STCHIP_Handle_t hChip, int TimeOut)
{
int Time=0,
CSMLocked=0;
while((!CSMLocked) && (Time < TimeOut))
{
CSMLocked = ChipGetField(hChip, FSTB0899_CSM_LOCK);
Time++;
}
return CSMLocked;
}
/* read uwp_state */
static int
FE_DVBS2_GetUWPstate(STCHIP_Handle_t hChip, int TimeOut)
{
int Time=0,
lock=0,
locked=0;
while((Time < TimeOut) && (lock == 0))
{
lock = ChipGetField(hChip, FSTB0899_UWP_LOCK);
Time++;
}
if(lock)
locked = 1;
return locked;
}
static int
FE_DVBS2_GetDataLock(STCHIP_Handle_t hChip, int TimeOut)
{
int Time = 0,
DataLocked = 0;
while((!DataLocked) && (Time < TimeOut))
{
DataLocked = ChipGetField(hChip, FSTB0899_LOCK);
Time++;
}
return DataLocked;
}
FE_DVBS2_State
FE_DVBS2_GetState(STCHIP_Handle_t hChip,int Timeout)
{
int tout, i = 0;
FE_DVBS2_State state = FE_DVBS2_NOAGC;
tout = Timeout;
do
{
if(FE_DVBS2_GetCSMLock(hChip, 1) != TRUE)
state = FE_DVBS2_NOCARRIER;
else
if((FE_DVBS2_GetUWPstate(hChip, 1) != TRUE))
state = FE_DVBS2_NOUWP;
else
if(FE_DVBS2_GetDataLock(hChip, 1) != TRUE)
state = FE_DVBS2_NODATA;
else
state = FE_DVBS2_DATAOK;
WAIT_N_MS(1);
i++;
}while((i < tout) && (state != FE_DVBS2_DATAOK));
return state;
}
/* read modecode */
u32
FE_DVBS2_GetModCod(STCHIP_Handle_t hChip)
{
return(ChipGetField(hChip,FSTB0899_UWP_DECODED_MODCODE) >> 2);
}
/* read EsNo */
S32
FE_DVBS2_GetUWPEsNo(STCHIP_Handle_t hChip,S32 Quant)
{
u32 tempus;
tempus = ChipGetField(hChip,FSTB0899_ESN0_ESR);
return tempus; /* to convert value to db tempus=(10*log10(tempus)/(quant^2)*/
/* with quant = UWP_ESN0_QUANT field value */
}
/*****************************************************
--FUNCTION :: FE_DVBS2_CarrierWidth
--ACTION :: Compute the width of the carrier
--PARAMS IN :: SymbolRate->Symbol rate of the carrier (Kbauds or Mbauds)
-- RollOff ->Rolloff * 100
--PARAMS OUT :: NONE
--RETURN :: Width of the carrier (KHz or MHz)
--***************************************************/
long
FE_DVBS2_CarrierWidth(long SymbolRate, FE_DVBS2_RRCAlpha_t Alpha)
{
long RollOff = 0;
switch(Alpha)
{
case RRC_20:
RollOff = 20;
break;
case RRC_25:
RollOff = 25;
break;
case RRC_35:
RollOff = 35;
break;
}
return (SymbolRate + (SymbolRate * RollOff) / 100);
}
u32
FE_DVBS2_GetSymbolRate(STCHIP_Handle_t hChip,u32 MasterClock)
{
u32 bTrNomFreq,
symbolRate,
decimRate,
intval1,intval2;
int div1, div2, rem1, rem2;
div1 = BTR_NCO_BITS/2;
div2 = BTR_NCO_BITS-div1-1;
bTrNomFreq = ChipGetOneRegister(hChip,RSTB0899_BTRNOMFREQ);
decimRate = ChipGetField(hChip,FSTB0899_DECIM_RATE);
decimRate = PowOf2(decimRate);
intval1 = MasterClock/PowOf2(div1);
intval2 = bTrNomFreq/PowOf2(div2);
/*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
rem1 = MasterClock%PowOf2(div1);
rem2 = bTrNomFreq%PowOf2(div2);
symbolRate = (intval1*intval2)+((intval1*rem2)/PowOf2(div2))+((intval2*rem1)/PowOf2(div1));
symbolRate /= decimRate;
return symbolRate;
}
void
FE_DVBS2_InitialCalculations(STCHIP_Handle_t hChip, FE_STB0899_DVBS2_InitParams_t *InitParams)
{
FE_DVBS2_UWPConfig_Params_t uwpParams;
FE_DVBS2_LoopBW_Params_t loopBW;
uwpParams.EsNoAve = ESNO_AVE;
uwpParams.EsNoQuant = ESNO_QUANT;
uwpParams.AveFramesCoarse = InitParams->AveFrameCoarse;
uwpParams.AveframesFine = InitParams->AveFramefine;
uwpParams.MissThreshold = MISS_THRESHOLD;
uwpParams.ThresholdAcq = UWP_THRESHOLD_ACQ;
uwpParams.ThresholdTrack = UWP_THRESHOLD_TRACK;
uwpParams.ThresholdSof = UWP_THRESHOLD_SOF;
uwpParams.SofSearchTimeout = SOF_SEARCH_TIMEOUT;
loopBW.LoopBwPercent = 60;
loopBW.SymbolRate = InitParams->SymbolRate;
loopBW.MasterClock = InitParams->MasterClock;
loopBW.Mode = InitParams->ModeMode;
loopBW.Zeta = 707;
loopBW.SymPeakVal = InitParams->AgcThreshold;/**5.76*/
/* config uwp and csm */
FE_DVBS2_ConfigUWP(hChip, uwpParams);
FE_DVBS2_AutoConfigCSM(hChip);
/* initialize BTR */
FE_DVBS2_SetSymbolRate(hChip, InitParams->SymbolRate, InitParams->MasterClock);
FE_DVBS2_SetBtrLoopBW(hChip, loopBW);
FE_DVBS2_BtrInit(hChip);
/* enable frequency adjustment and set spectral inversion */
ChipSetOneRegister(hChip, RSTB0899_DMDCNTRL2, (2 | (InitParams->SpectralInv << 2)));
/* disable CRL */
ChipSetOneRegister(hChip, RSTB0899_CRLFREQINIT, 1 << 30);
ChipSetOneRegister(hChip, RSTB0899_CRLLOOPGAIN, 0);
ChipSetOneRegister(hChip, RSTB0899_CRLPHSINIT, 1 << 30);
ChipSetOneRegister(hChip, RSTB0899_CRLPHSINIT, 0);
}
void
FE_DVBS2_Reacquire(STCHIP_Handle_t hChip, FE_DVBS2_ReacquireParams_t * ReacquireParams)
{
S32 numSteps,
freqStepSize,
acqcntrl2;
/*disable input buff*/
ChipSetOneRegister(hChip, RSTB0899_INTBUFCTRL, 0x00);
/* set demod soft reset*/
ChipSetOneRegister(hChip, RSTB0899_RESETCNTRL, 0x1);
FE_DVBS2_Reset(hChip);
/*release demod soft reset */
ChipSetOneRegister(hChip, RSTB0899_RESETCNTRL, 0);
/* reset decoder */
ChipSetOneRegister(hChip, RSTB0899_LDPCDECRST, 1);
ChipSetOneRegister(hChip, RSTB0899_LDPCDECRST, 0);
if(ReacquireParams->AcqMode == NO_SEARCH)
{
FE_DVBS2_StartUWP(hChip);
}
else
{
/*numSteps =(ReacquireParams->FreqRange*100)/((ReacquireParams->SymbolRate/1000000)*ReacquireParams->StepSize);
numSteps=(numSteps+5)/10;
freqStepSize =(ReacquireParams->StepSize * (1<<17))/10;*/
if(ReacquireParams->SymbolRate / 1000000 >= 15)
freqStepSize = (1 << 17) / 5;
else if(ReacquireParams->SymbolRate/ 1000000 >= 10)
freqStepSize = (1 << 17) / 7;
else if(ReacquireParams->SymbolRate / 1000000 >= 5)
freqStepSize = (1 << 17) / 10;
else
freqStepSize = (1 << 17) / 3;
numSteps = (10 * ReacquireParams->FreqRange * (1 << 17)) / (freqStepSize * (ReacquireParams->SymbolRate / 1000000));
numSteps = (numSteps + 6) / 10;
numSteps = (numSteps == 0) ? 1 : numSteps;
if(ReacquireParams->Zigzag)
if(numSteps % 2 == 0)
FE_DVBS2_SetCarrierFreq(hChip, ReacquireParams->CenterFreq - (ReacquireParams->StepSize * (ReacquireParams->SymbolRate / 20000000)), (ReacquireParams->MasterClock) / 1000000);
else
FE_DVBS2_SetCarrierFreq(hChip, ReacquireParams->CenterFreq, (ReacquireParams->MasterClock) / 1000000);
else
FE_DVBS2_SetCarrierFreq(hChip, ReacquireParams->CenterFreq - (ReacquireParams->FreqRange / 2),(ReacquireParams->MasterClock) / 1000000);
/*Set Carrier Search params (zigzag, num steps and freq step size*/
acqcntrl2 = (ReacquireParams->Zigzag << 25) | (numSteps << 17) | (freqStepSize);
ChipSetOneRegister(hChip, RSTB0899_ACQCNTRL2, acqcntrl2);
/* Equalizer Init */
ChipSetFieldImage(hChip, FSTB0899_EQ_INIT, 1);
ChipSetRegisters(hChip, RSTB0899_EQUILIZERINIT, 1);
ChipSetFieldImage(hChip, FSTB0899_EQ_INIT, 0);
ChipSetRegisters(hChip, RSTB0899_EQUILIZERINIT, 1);
/* Equalizer Disable update */
ChipSetFieldImage(hChip, FSTB0899_EQ_DISABLE_UPDATE, 0);
ChipSetRegisters(hChip, RSTB0899_EQCNTL, 1);
/* start acquistion process */
ChipSetOneRegister(hChip, RSTB0899_ACQUIRETRIG, 1);
ChipSetOneRegister(hChip, RSTB0899_LOCKLOST, 0);
/*activate input buff*/
ChipSetOneRegister(hChip, RSTB0899_INTBUFCTRL, 0x0a);
/*Reset Packet Delin*/
ChipSetField(hChip, FSTB0899_ALGOSWRST, 1);
ChipSetField(hChip, FSTB0899_ALGOSWRST, 0);
ChipSetField(hChip, FSTB0899_HYSTSWRST, 1);
ChipSetField(hChip, FSTB0899_HYSTSWRST, 0);
ChipSetOneRegister(hChip, RSTB0899_PDELCTRL, 0x4a);
/*Reset stream merger*/
ChipSetField(hChip, FSTB0899_FRESRS, 1);
ChipSetField(hChip, FSTB0899_FRESRS, 0);
}
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