class.ptf

i2c IP核 i2c.master i2c.mater.v

CLASS opencores_i2c_master
{
   ASSOCIATED_FILES 
   {
      Add_Program = "";
      Edit_Program = "";
      Generator_Program = "";
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "OpenCores I2C Master";
         technology = "Communication";
      }
   }
   DEFAULT_GENERATOR 
   {
      top_module_name = "oc_i2c_master";
      black_box = "0";
      vhdl_synthesis_files = "i2c_master_bit_ctrl.vhd, i2c_master_byte_ctrl.vhd, i2c_master_top.vhd, oc_i2c_master.vhd";
      verilog_synthesis_files="";
      black_box_files="";
   }
   MODULE_DEFAULTS 
   {
      class = "opencores_i2c_master";
      class_version = "2.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Date_Modified = "--unknown--";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      PORT_WIRING 
      {
        PORT scl_pad_io
        {
           direction = "inout";
           width     = "1";
        }
        PORT sda_pad_io
        {
           direction = "inout";
           width     = "1";
        }
      }
      SIMULATION
      {
         DISPLAY
         {
            SIGNAL a
            {
               name = " I2C Master";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "scl_pad_io";
            }
            SIGNAL c
            {
               name = "sda_pad_io";
            }
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Setup_Time = "0";
            Hold_Time = "0";
            Is_Memory_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT wb_clk_i
            {
               width = "1";
               direction = "input";
               type = "clk";
            }
            PORT wb_rst_i
            {
               width = "1";
               direction = "input";
               type = "reset";
            }
            PORT wb_adr_i
            {
               width = "3";
               direction = "input";
               type = "address";
            }
            PORT wb_dat_i
            {
               width = "32";
               direction = "input";
               type = "writedata";
            }
            PORT wb_dat_o
            {
               width = "32";
               direction = "output";
               type = "readdata";
            }
            PORT wb_err_o
            {
               width = "1";
               direction = "output";
               type = "wishbone_err";
            }
            PORT wb_we_i
            {
               width = "1";
               direction = "input";
               type = "write";
            }
            PORT wb_stb_i
            {
               width = "1";
               direction = "input";
               type = "chipselect";
            }
            PORT wb_cyc_i
            {
               width = "1";
               direction = "input";
               type = "chipselect";
            }
            PORT wb_ack_o
            {
               width = "1";
               direction = "output";
               type = "waitrequest_n";
            }
            PORT wb_inta_o
            {
               width = "1";
               direction = "output";
               type = "irq";
            }
         }
      }
   }
}