apollon.c

uboot详细解读可用启动引导LINUX2.6内核

/*
 * (C) Copyright 2005-2007
 * Samsung Electronics.
 * Kyungmin Park <[e-mail]>
 *
 * Derived from omap2420
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/mem.h>
#include <asm/mach-types.h>

void wait_for_command_complete(unsigned int wd_base);

DECLARE_GLOBAL_DATA_PTR;

#define write_config_reg(reg, value)					\
do {									\
	writeb(value, reg);						\
} while (0)

#define mask_config_reg(reg, mask)					\
do {									\
	char value = readb(reg) & ~(mask);				\
	writeb(value, reg);						\
} while (0)

/*******************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 ******************************************************/
static inline void delay(unsigned long loops)
{
	__asm__("1:\n" "subs %0, %1, #1\n"
		  "bne 1b":"=r" (loops):"0"(loops));
}

/*****************************************
 * Routine: board_init
 * Description: Early hardware init.
 *****************************************/
int board_init(void)
{
	gpmc_init();		/* in SRAM or SDRM, finish GPMC */

	gd->bd->bi_arch_number = 919;
	/* adress of boot parameters */
	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);

	return 0;
}

/**********************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 * - Called path is with sram stack.
 **********************************************************/
void s_init(void)
{
	watchdog_init();
	set_muxconf_regs();
	delay(100);

	peripheral_enable();
	icache_enable();
}

/*******************************************************
 * Routine: misc_init_r
 * Description: Init ethernet (done here so udelay works)
 ********************************************************/
int misc_init_r(void)
{
	ether_init();		/* better done here so timers are init'ed */
	return (0);
}

/****************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************/
void watchdog_init(void)
{
	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
	 * The ROM takes care of the secure one. Of the 3 GP ones,
	 * 1 can reset us directly, the other 2 only generate MPU interrupts.
	 */
	__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
	wait_for_command_complete(WD2_BASE);
	__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);

#define MPU_WD_CLOCKED 1
#if MPU_WD_CLOCKED
	/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
	__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
	wait_for_command_complete(WD3_BASE);
	__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);

	__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
	wait_for_command_complete(WD4_BASE);
	__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
#endif
}

/******************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 ******************************************************/
void wait_for_command_complete(unsigned int wd_base)
{
	int pending = 1;
	do {
		pending = __raw_readl(wd_base + WWPS);
	} while (pending);
}

/*******************************************************************
 * Routine:ether_init
 * Description: take the Ethernet controller out of reset and wait
 *		   for the EEPROM load to complete.
 ******************************************************************/
void ether_init(void)
{
#ifdef CONFIG_DRIVER_LAN91C96
	int cnt = 20;

	__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2);	/*protect->gpio74 */

	__raw_writew(0x0, LAN_RESET_REGISTER);
	do {
		__raw_writew(0x1, LAN_RESET_REGISTER);
		udelay(100);
		if (cnt == 0)
			goto eth_reset_err_out;
		--cnt;
	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);

	cnt = 20;

	do {
		__raw_writew(0x0, LAN_RESET_REGISTER);
		udelay(100);
		if (cnt == 0)
			goto eth_reset_err_out;
		--cnt;
	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
	udelay(1000);

	mask_config_reg(ETH_CONTROL_REG, 0x01);
	udelay(1000);

eth_reset_err_out:
	return;
#endif
}

/**********************************************
 * Routine: dram_init
 * Description: sets uboots idea of sdram size
 **********************************************/
int dram_init(void)
{
	unsigned int size0 = 0, size1 = 0;
	u32 mtype, btype, rev = 0, cpu = 0;
#define NOT_EARLY 0

	btype = get_board_type();
	mtype = get_mem_type();
	rev = get_cpu_rev();
	cpu = get_cpu_type();

	display_board_info(btype);

	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
		/* init other chip select */
		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
	}

	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
	size1 = get_sdr_cs_size(SDRC_CS1_OSET);

	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = size0;
#if CONFIG_NR_DRAM_BANKS > 1
	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
	gd->bd->bi_dram[1].size = size1;
#endif

	return 0;
}

/**********************************************************
 * Routine: set_muxconf_regs
 * Description: Setting up the configuration Mux registers
 *              specific to the hardware
 *********************************************************/
void set_muxconf_regs(void)
{
	muxSetupSDRC();
	muxSetupGPMC();
	muxSetupUsb0();		/* USB Device */
	muxSetupUsbHost();	/* USB Host */
	muxSetupUART1();
	muxSetupLCD();
	muxSetupMMCSD();
	muxSetupTouchScreen();
}

/*****************************************************************
 * Routine: peripheral_enable
 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 ******************************************************************/