4xx_pcie.c

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/*
 * (C) Copyright 2006 - 2008
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * Copyright (c) 2005 Cisco Systems.  All rights reserved.
 * Roland Dreier <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 */

/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif

#include <common.h>
#include <pci.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm-ppc/io.h>

#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) ||	\
    defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
    defined(CONFIG_PCI)

#include <asm/4xx_pcie.h>

enum {
	PTYPE_ENDPOINT		= 0x0,
	PTYPE_LEGACY_ENDPOINT	= 0x1,
	PTYPE_ROOT_PORT		= 0x4,

	LNKW_X1			= 0x1,
	LNKW_X4			= 0x4,
	LNKW_X8			= 0x8
};

static int validate_endpoint(struct pci_controller *hose)
{
	if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
		return (is_end_point(0));
	else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
		return (is_end_point(1));
#if CFG_PCIE_NR_PORTS > 2
	else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
		return (is_end_point(2));
#endif

	return 0;
}

static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
{
	u8 *base = (u8*)hose->cfg_data;

	/* use local configuration space for the first bus */
	if (PCI_BUS(devfn) == 0) {
		if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
			base = (u8*)CFG_PCIE0_XCFGBASE;
		if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
			base = (u8*)CFG_PCIE1_XCFGBASE;
#if CFG_PCIE_NR_PORTS > 2
		if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
			base = (u8*)CFG_PCIE2_XCFGBASE;
#endif
	}

	return base;
}

static void pcie_dmer_disable(void)
{
	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
#if CFG_PCIE_NR_PORTS > 2
	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
#endif
}

static void pcie_dmer_enable(void)
{
	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
#if CFG_PCIE_NR_PORTS > 2
	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
#endif
}

static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
	int offset, int len, u32 *val) {

	u8 *address;
	*val = 0;

	if (validate_endpoint(hose))
		return 0;		/* No upstream config access */

	/*
	 * Bus numbers are relative to hose->first_busno
	 */
	devfn -= PCI_BDF(hose->first_busno, 0, 0);

	/*
	 * NOTICE: configuration space ranges are currenlty mapped only for
	 * the first 16 buses, so such limit must be imposed. In case more
	 * buses are required the TLB settings in board/amcc/<board>/init.S
	 * need to be altered accordingly (one bus takes 1 MB of memory space).
	 */
	if (PCI_BUS(devfn) >= 16)
		return 0;

	/*
	 * Only single device/single function is supported for the primary and
	 * secondary buses of the 440SPe host bridge.
	 */
	if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
		((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
		return 0;

	address = pcie_get_base(hose, devfn);
	offset += devfn << 4;

	/*
	 * Reading from configuration space of non-existing device can
	 * generate transaction errors. For the read duration we suppress
	 * assertion of machine check exceptions to avoid those.
	 */
	pcie_dmer_disable ();

	debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
	switch (len) {
	case 1:
		*val = in_8(hose->cfg_data + offset);
		break;
	case 2:
		*val = in_le16((u16 *)(hose->cfg_data + offset));
		break;
	default:
		*val = in_le32((u32*)(hose->cfg_data + offset));
		break;
	}

	pcie_dmer_enable ();

	return 0;
}

static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
	int offset, int len, u32 val) {

	u8 *address;

	if (validate_endpoint(hose))
		return 0;		/* No upstream config access */

	/*
	 * Bus numbers are relative to hose->first_busno
	 */
	devfn -= PCI_BDF(hose->first_busno, 0, 0);

	/*
	 * Same constraints as in pcie_read_config().
	 */
	if (PCI_BUS(devfn) >= 16)
		return 0;

	if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
		((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
		return 0;

	address = pcie_get_base(hose, devfn);
	offset += devfn << 4;

	/*
	 * Suppress MCK exceptions, similar to pcie_read_config()
	 */
	pcie_dmer_disable ();

	switch (len) {
	case 1:
		out_8(hose->cfg_data + offset, val);
		break;
	case 2:
		out_le16((u16 *)(hose->cfg_data + offset), val);
		break;
	default:
		out_le32((u32 *)(hose->cfg_data + offset), val);
		break;
	}

	pcie_dmer_enable ();

	return 0;
}

int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
{
	u32 v;
	int rv;

	rv = pcie_read_config(hose, dev, offset, 1, &v);
	*val = (u8)v;
	return rv;
}

int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
{
	u32 v;
	int rv;

	rv = pcie_read_config(hose, dev, offset, 2, &v);
	*val = (u16)v;
	return rv;
}

int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
{
	u32 v;
	int rv;

	rv = pcie_read_config(hose, dev, offset, 3, &v);
	*val = (u32)v;
	return rv;
}

int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
{
	return pcie_write_config(hose,(u32)dev,offset,1,val);
}

int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
{
	return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
}

int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
{
	return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
}

#if defined(CONFIG_440SPE)
static void ppc4xx_setup_utl(u32 port) {

	volatile void *utl_base = NULL;

	/*
	 * Map UTL registers
	 */
	switch (port) {
	case 0:
		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
		break;

	case 1:
		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
		break;

	case 2:
		mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
		mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
		mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
		mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
		break;
	}
	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);

	/*
	 * Set buffer allocations and then assert VRB and TXE.
	 */
	out_be32(utl_base + PEUTL_OUTTR,   0x08000000);
	out_be32(utl_base + PEUTL_INTR,    0x02000000);
	out_be32(utl_base + PEUTL_OPDBSZ,  0x10000000);
	out_be32(utl_base + PEUTL_PBBSZ,   0x53000000);
	out_be32(utl_base + PEUTL_IPHBSZ,  0x08000000);
	out_be32(utl_base + PEUTL_IPDBSZ,  0x10000000);
	out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
	out_be32(utl_base + PEUTL_PCTL,    0x80800066);
}

static int check_error(void)
{
	u32 valPE0, valPE1, valPE2;
	int err = 0;

	/* SDR0_PEGPLLLCT1 reset */
	if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
		printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);

	valPE0 = SDR_READ(PESDR0_RCSSET);
	valPE1 = SDR_READ(PESDR1_RCSSET);
	valPE2 = SDR_READ(PESDR2_RCSSET);

	/* SDR0_PExRCSSET rstgu */
	if (!(valPE0 & 0x01000000) ||
	    !(valPE1 & 0x01000000) ||
	    !(valPE2 & 0x01000000)) {
		printf("PCIE:  SDR0_PExRCSSET rstgu error\n");
		err = -1;
	}

	/* SDR0_PExRCSSET rstdl */
	if (!(valPE0 & 0x00010000) ||
	    !(valPE1 & 0x00010000) ||
	    !(valPE2 & 0x00010000)) {
		printf("PCIE:  SDR0_PExRCSSET rstdl error\n");
		err = -1;
	}

	/* SDR0_PExRCSSET rstpyn */
	if ((valPE0 & 0x00001000) ||
	    (valPE1 & 0x00001000) ||
	    (valPE2 & 0x00001000)) {
		printf("PCIE:  SDR0_PExRCSSET rstpyn error\n");
		err = -1;
	}

	/* SDR0_PExRCSSET hldplb */
	if ((valPE0 & 0x10000000) ||
	    (valPE1 & 0x10000000) ||
	    (valPE2 & 0x10000000)) {
		printf("PCIE:  SDR0_PExRCSSET hldplb error\n");
		err = -1;
	}

	/* SDR0_PExRCSSET rdy */
	if ((valPE0 & 0x00100000) ||
	    (valPE1 & 0x00100000) ||
	    (valPE2 & 0x00100000)) {
		printf("PCIE:  SDR0_PExRCSSET rdy error\n");
		err = -1;
	}

	/* SDR0_PExRCSSET shutdown */
	if ((valPE0 & 0x00000100) ||
	    (valPE1 & 0x00000100) ||
	    (valPE2 & 0x00000100)) {
		printf("PCIE:  SDR0_PExRCSSET shutdown error\n");
		err = -1;
	}
	return err;
}

/*
 * Initialize PCI Express core
 */
int ppc4xx_init_pcie(void)
{
	int time_out = 20;

	/* Set PLL clock receiver to LVPECL */
	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);

	if (check_error())
		return -1;

	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
	{
		printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
		       SDR_READ(PESDR0_PLLLCT2));
		return -1;
	}
	/* De-assert reset of PCIe PLL, wait for lock */
	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
	udelay(3);

	while (time_out) {
		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {