ppc405.h
来自「uboot详细解读可用启动引导LINUX2.6内核」· C头文件 代码 · 共 1,367 行 · 第 1/5 页
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#define UIC_GPTCMPT8 0x00800000 /* */#define UIC_GPTCMPT9 0x00400000 /* */#define UIC_PCIE1AL 0x00200000 /* */#define UIC_PCIE1VPD 0x00100000 /* */#define UIC_RPCE1HRST 0x00080000 /* */#define UIC_FPCE1HRST 0x00040000 /* */#define UIC_PCIE1TCR 0x00020000 /* */#define UIC_PCIE1VC0 0x00010000 /* */#define UIC_GPTCMPT3 0x00008000 /* */#define UIC_GPTCMPT4 0x00004000 /* */#define UIC_EIRQ7 0x00002000 /* */#define UIC_EIRQ8 0x00001000 /* */#define UIC_EIRQ9 0x00000800 /* */#define UIC_GPTCMP5 0x00000400 /* */#define UIC_GPTCMP6 0x00000200 /* */#define UIC_GPTCMP7 0x00000100 /* */#define UIC_SROM 0x00000080 /* SERIAL ROM*/#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/#define UIC_EIRQ2 0x00000020 /* */#define UIC_EIRQ5 0x00000010 /* */#define UIC_EIRQ6 0x00000008 /* */#define UIC_EMAC0WAKE 0x00000004 /* */#define UIC_EIRQ1 0x00000002 /* */#define UIC_EMAC1WAKE 0x00000001 /* */#define UIC_MAL_SERR UIC_MS /* MAL SERR */#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE *//* UIC 2 */#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/#define UIC_DDRMCUE 0x04000000 /* */#define UIC_DDRMCCE 0x02000000 /* */#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/#define UIC_USBWAKE 0x00000002 /* USB wakup*/#define UIC_USBOTG 0x00000001 /* USB OTG*/#define UIC_ETH0 UIC_ENET#define UIC_ETH1 UIC_ENET1#else /* !defined(CONFIG_405EZ) */#define UIC_UART0 0x80000000 /* UART 0 */#define UIC_UART1 0x40000000 /* UART 1 */#define UIC_IIC 0x20000000 /* IIC */#define UIC_EXT_MAST 0x10000000 /* External Master */#define UIC_PCI 0x08000000 /* PCI write to command reg */#define UIC_DMA0 0x04000000 /* DMA chan. 0 */#define UIC_DMA1 0x02000000 /* DMA chan. 1 */#define UIC_DMA2 0x01000000 /* DMA chan. 2 */#define UIC_DMA3 0x00800000 /* DMA chan. 3 */#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */#define UIC_MAL_SERR 0x00200000 /* MAL SERR */#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */#define UIC_ENET 0x00010000 /* Ethernet0 */#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */#define UIC_PCI_PM 0x00002000 /* PCI Power Management */#define UIC_EXT0 0x00000040 /* External interrupt 0 */#define UIC_EXT1 0x00000020 /* External interrupt 1 */#define UIC_EXT2 0x00000010 /* External interrupt 2 */#define UIC_EXT3 0x00000008 /* External interrupt 3 */#define UIC_EXT4 0x00000004 /* External interrupt 4 */#define UIC_EXT5 0x00000002 /* External interrupt 5 */#define UIC_EXT6 0x00000001 /* External interrupt 6 */#endif /* defined(CONFIG_405EZ) *//****************************************************************************** * External Bus Controller (EBC) *****************************************************************************//* Bank Configuration Register */#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ EBC_BXCR_BAS_MASK) << 0)#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)/* Bank Access Parameter Register */#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ (static_cast(unsigned long, n)) \ & 0xFF)#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ (static_cast(unsigned long, n)) \ & 0x1F)#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ (static_cast(unsigned long, n)) \ & 0x7)#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ (static_cast(unsigned long, n)) \ & 0x3)#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ (static_cast(unsigned long, n)) \ & 0x3)#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ (static_cast(unsigned long, n)) \ & 0x3)#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ (static_cast(unsigned long, n)) \ & 0x3)#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ (static_cast(unsigned long, n)) \ & 0x7)#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)/* Configuration Register */#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0)#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1)#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ (static_cast(unsigned long, n)) \ & 0x1F)#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)#ifndef CONFIG_405EP/****************************************************************************** * Decompression Controller ******************************************************************************/#define DECOMP_DCR_BASE 0x14#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ /* values for kiar register - indirect addressing of these regs */ #define kitor0 0x00 /* index table origin register 0 */ #define kitor1 0x01 /* index table origin register 1 */ #define kitor2 0x02 /* index table origin register 2 */ #define kitor3 0x03 /* index table origin register 3 */ #define kaddr0 0x04 /* address decode definition regsiter 0 */ #define kaddr1 0x05 /* address decode definition regsiter 1 */ #define kconf 0x40 /* decompression core config register */ #define kid 0x41 /* decompression core ID register */ #define kver 0x42 /* decompression core version # reg */ #define kpear 0x50 /* bus error addr reg (PLB addr) */ #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ #define kesr0s 0x53 /* bus error status reg 0 (set) */ /* There are 0x400 of the following registers, from krom0 to krom3ff*/ /* Only the first one is given here. */ #define krom0 0x400 /* SRAM/ROM read/write */#endif/****************************************************************************** * Power Management ******************************************************************************/#ifdef CONFIG_405EX#define POWERMAN_DCR_BASE 0xb0#else#define POWERMAN_DCR_BASE 0xb8#endif#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force *//****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ #define pb2cr 0x02 /* periph bank 2 config reg */ #define pb3cr 0x03 /* periph bank 3 config reg */ #define pb4cr 0x04 /* periph bank 4 config reg */#ifndef CONFIG_405EP #define pb5cr 0x05 /* periph bank 5 config reg */ #define pb6cr 0x06 /* periph bank 6 config reg */ #define pb7cr 0x07 /* periph bank 7 config reg */#endif #define pb0ap 0x10 /* periph bank 0 access parameters */ #define pb1ap 0x11 /* periph bank 1 access parameters */ #define pb2ap 0x12 /* periph bank 2 access parameters */ #define pb3ap 0x13 /* periph bank 3 access parameters */ #define pb4ap 0x14 /* periph bank 4 access parameters */#ifndef CONFIG_405EP #define pb5ap 0x15 /* periph bank 5 access parameters */ #define pb6ap 0x16 /* periph bank 6 access parameters */ #define pb7ap 0x17 /* periph bank 7 access parameters */#endif #define pbear 0x20 /* periph bus error addr reg */ #define pbesr0 0x21 /* periph bus error status reg 0 */ #define pbesr1 0x22 /* periph bus error status reg 1 */ #define epcr 0x23 /* external periph control reg */⌨️ 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