ppc405.h

来自「uboot详细解读可用启动引导LINUX2.6内核」· C头文件 代码 · 共 1,367 行 · 第 1/5 页

/*----------------------------------------------------------------------------+
|
|	This source code has been made available to you by IBM on an AS-IS
|	basis.	Anyone receiving this source is licensed under IBM
|	copyrights to use it in any way he or she deems fit, including
|	copying it, modifying it, compiling it, and redistributing it either
|	with or without modifications.	No license under IBM patents or
|	patent applications is to be implied by the copyright license.
|
|	Any user of this software should understand that IBM cannot provide
|	technical support for this software and will not be responsible for
|	any consequences resulting from the use of this software.
|
|	Any person who transfers this source code or any derivative work
|	must include the IBM copyright notice, this paragraph, and the
|	preceding two paragraphs in the transferred software.
|
|	COPYRIGHT   I B M   CORPORATION 1999
|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/

#ifndef	__PPC405_H__
#define __PPC405_H__

/* Define bits and masks for real-mode storage attribute control registers */
#define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
#define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)

#ifndef CONFIG_IOP480
#define CFG_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs	*/
#else
#define CFG_DCACHE_SIZE		(2 << 10)	/* For PLX IOP480 (403)	*/
#endif

/*--------------------------------------------------------------------- */
/* Special Purpose Registers						*/
/*--------------------------------------------------------------------- */
	#define  srr2  0x3de	  /* save/restore register 2 */
	#define  srr3  0x3df	  /* save/restore register 3 */

	/*
	 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
	 * exception for the exact same purposes - let's alias them and have a
	 * common handling in crit_return() and CRIT_EXCEPTION
	 */
	#define  csrr0 srr2
	#define  csrr1 srr3

	#define  dbsr  0x3f0	  /* debug status register */
	#define  dbcr0 0x3f2	  /* debug control register 0 */
	#define  dbcr1 0x3bd	  /* debug control register 1 */
	#define  iac1  0x3f4	  /* instruction address comparator 1 */
	#define  iac2  0x3f5	  /* instruction address comparator 2 */
	#define  iac3  0x3b4	  /* instruction address comparator 3 */
	#define  iac4  0x3b5	  /* instruction address comparator 4 */
	#define  dac1  0x3f6	  /* data address comparator 1 */
	#define  dac2  0x3f7	  /* data address comparator 2 */
	#define  dccr  0x3fa	  /* data cache control register */
	#define  iccr  0x3fb	  /* instruction cache control register */
	#define  esr   0x3d4	  /* execption syndrome register */
	#define  dear  0x3d5	  /* data exeption address register */
	#define  evpr  0x3d6	  /* exeption vector prefix register */
	#define  tsr   0x3d8	  /* timer status register */
	#define  tcr   0x3da	  /* timer control register */
	#define  pit   0x3db	  /* programmable interval timer */
	#define  sgr   0x3b9	  /* storage guarded reg      */
	#define  dcwr  0x3ba	  /* data cache write-thru reg*/
	#define  sler  0x3bb	  /* storage little-endian reg */
	#define  cdbcr 0x3d7	  /* cache debug cntrl reg    */
	#define  icdbdr 0x3d3	  /* instr cache dbug data reg*/
	#define  ccr0  0x3b3	  /* core configuration register */
	#define  dvc1  0x3b6	  /* data value compare register 1 */
	#define  dvc2  0x3b7	  /* data value compare register 2 */
	#define  pid   0x3b1	  /* process ID */
	#define  su0r  0x3bc	  /* storage user-defined register 0 */
	#define  zpr   0x3b0	  /* zone protection regsiter */

	#define  tbl   0x11c	  /* time base lower - privileged write */
	#define  tbu   0x11d	  /* time base upper - privileged write */

	#define  sprg4r 0x104	  /* Special purpose general 4 - read only */
	#define  sprg5r 0x105	  /* Special purpose general 5 - read only */
	#define  sprg6r 0x106	  /* Special purpose general 6 - read only */
	#define  sprg7r 0x107	  /* Special purpose general 7 - read only */
	#define  sprg4w 0x114	  /* Special purpose general 4 - write only */
	#define  sprg5w 0x115	  /* Special purpose general 5 - write only */
	#define  sprg6w 0x116	  /* Special purpose general 6 - write only */
	#define  sprg7w 0x117	  /* Special purpose general 7 - write only */

/******************************************************************************
 * Special for PPC405GP
 ******************************************************************************/

/******************************************************************************
 * DMA
 ******************************************************************************/
#define DMA_DCR_BASE 0x100
#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
#define dmada0	(DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
#define dmasa0	(DMA_DCR_BASE+0x03)  /* DMA source address register 0	     */
#define dmasb0	(DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
#define dmada1	(DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
#define dmasa1	(DMA_DCR_BASE+0x0b)  /* DMA source address register 1	     */
#define dmasb1	(DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
#define dmada2	(DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
#define dmasa2	(DMA_DCR_BASE+0x13)  /* DMA source address register 2	     */
#define dmasb2	(DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 3	     */
#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 3		     */
#define dmada3	(DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
#define dmasa3	(DMA_DCR_BASE+0x1b)  /* DMA source address register 3	     */
#define dmasb3	(DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
#define dmaadr	(DMA_DCR_BASE+0x24)  /* DMA address decode register	     */

/******************************************************************************
 * Universal interrupt controller
 ******************************************************************************/
#define UIC_SR	0x0			/* UIC status			   */
#define UIC_ER	0x2			/* UIC enable			   */
#define UIC_CR	0x3			/* UIC critical			   */
#define UIC_PR	0x4			/* UIC polarity			   */
#define UIC_TR	0x5			/* UIC triggering		   */
#define UIC_MSR 0x6			/* UIC masked status		   */
#define UIC_VR	0x7			/* UIC vector			   */
#define UIC_VCR 0x8			/* UIC vector configuration	   */

#define UIC_DCR_BASE 0xc0
#define UIC0_DCR_BASE UIC_DCR_BASE
#define uicsr	     (UIC_DCR_BASE+0x0)  /* UIC status			     */
#define uicsrs	     (UIC_DCR_BASE+0x1)  /* UIC status set		     */
#define uicer	     (UIC_DCR_BASE+0x2)  /* UIC enable			     */
#define uiccr	     (UIC_DCR_BASE+0x3)  /* UIC critical		     */
#define uicpr	     (UIC_DCR_BASE+0x4)  /* UIC polarity		     */
#define uictr	     (UIC_DCR_BASE+0x5)  /* UIC triggering		     */
#define uicmsr	     (UIC_DCR_BASE+0x6)  /* UIC masked status		     */
#define uicvr	     (UIC_DCR_BASE+0x7)  /* UIC vector			     */
#define uicvcr	     (UIC_DCR_BASE+0x8)  /* UIC vector configuration	     */

#if defined(CONFIG_405EX)
#define uic0sr	      uicsr		/* UIC status		 */
#define uic0srs       uicsrs		/* UIC status set	 */
#define uic0er	      uicer		/* UIC enable		 */
#define uic0cr	      uiccr		/* UIC critical		 */
#define uic0pr	      uicpr		/* UIC polarity		 */
#define uic0tr	      uictr		/* UIC triggering	 */
#define uic0msr       uicmsr		/* UIC masked status	 */
#define uic0vr	      uicvr		/* UIC vector		 */
#define uic0vcr       uicvcr		/* UIC vector configuration*/

#define UIC_DCR_BASE1 0xd0
#define UIC1_DCR_BASE 0xd0
#define uic1sr	      (UIC_DCR_BASE1+0x0)  /* UIC status	    */
#define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set	    */
#define uic1er	      (UIC_DCR_BASE1+0x2)  /* UIC enable	    */
#define uic1cr	      (UIC_DCR_BASE1+0x3)  /* UIC critical	    */
#define uic1pr	      (UIC_DCR_BASE1+0x4)  /* UIC polarity	    */
#define uic1tr	      (UIC_DCR_BASE1+0x5)  /* UIC triggering	    */
#define uic1msr       (UIC_DCR_BASE1+0x6)  /* UIC masked status     */
#define uic1vr	      (UIC_DCR_BASE1+0x7)  /* UIC vector	    */
#define uic1vcr       (UIC_DCR_BASE1+0x8)  /* UIC vector configuration*/

#define UIC_DCR_BASE2 0xe0
#define UIC2_DCR_BASE 0xe0
#define uic2sr	      (UIC_DCR_BASE2+0x0)  /* UIC status	    */
#define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set	    */
#define uic2er	      (UIC_DCR_BASE2+0x2)  /* UIC enable	    */
#define uic2cr	      (UIC_DCR_BASE2+0x3)  /* UIC critical	    */
#define uic2pr	      (UIC_DCR_BASE2+0x4)  /* UIC polarity	    */
#define uic2tr	      (UIC_DCR_BASE2+0x5)  /* UIC triggering	    */
#define uic2msr       (UIC_DCR_BASE2+0x6)  /* UIC masked status     */
#define uic2vr	      (UIC_DCR_BASE2+0x7)  /* UIC vector	    */
#define uic2vcr       (UIC_DCR_BASE2+0x8)  /* UIC vector configuration*/
#endif

/*-----------------------------------------------------------------------------+
|  Universal interrupt controller interrupts
+-----------------------------------------------------------------------------*/
#if defined(CONFIG_405EZ)
#define UIC_DMA0	0x80000000	/* DMA chan. 0			*/
#define UIC_DMA1	0x40000000	/* DMA chan. 1			*/
#define UIC_DMA2	0x20000000	/* DMA chan. 2			*/
#define UIC_DMA3	0x10000000	/* DMA chan. 3			*/
#define UIC_1588	0x08000000	/* IEEE 1588 network synchronization */
#define UIC_UART0	0x04000000	/* UART 0			*/
#define UIC_UART1	0x02000000	/* UART 1			*/
#define UIC_CAN0	0x01000000	/* CAN 0			*/
#define UIC_CAN1	0x00800000	/* CAN 1			*/
#define UIC_SPI		0x00400000	/* SPI				*/
#define UIC_IIC		0x00200000	/* IIC				*/
#define UIC_CHT0	0x00100000	/* Chameleon timer high pri interrupt */
#define UIC_CHT1	0x00080000	/* Chameleon timer high pri interrupt */
#define UIC_USBH1	0x00040000	/* USB Host 1			*/
#define UIC_USBH2	0x00020000	/* USB Host 2			*/
#define UIC_USBDEV	0x00010000	/* USB Device			*/
#define UIC_ENET	0x00008000	/* Ethernet interrupt status	*/
#define UIC_ENET1	0x00008000	/* dummy define			*/
#define UIC_EMAC_WAKE	0x00004000	/* EMAC wake up			*/

#define UIC_MADMAL	0x00002000	/* Logical OR of following MadMAL int */
#define UIC_MAL_SERR	0x00002000	/*   MAL SERR			*/
#define UIC_MAL_TXDE	0x00002000	/*   MAL TXDE			*/
#define UIC_MAL_RXDE	0x00002000	/*   MAL RXDE			*/

#define UIC_MAL_TXEOB	0x00001000	/* MAL TXEOB			*/
#define UIC_MAL_TXEOB1	0x00000800	/* MAL TXEOB1			*/
#define UIC_MAL_RXEOB	0x00000400	/* MAL RXEOB			*/
#define UIC_NAND	0x00000200	/* NAND Flash controller	*/
#define UIC_ADC		0x00000100	/* ADC				*/
#define UIC_DAC		0x00000080	/* DAC				*/
#define UIC_OPB2PLB	0x00000040	/* OPB to PLB bridge interrupt	*/
#define UIC_RESERVED0	0x00000020	/* Reserved			*/
#define UIC_EXT0	0x00000010	/* External  interrupt 0	*/
#define UIC_EXT1	0x00000008	/* External  interrupt 1	*/
#define UIC_EXT2	0x00000004	/* External  interrupt 2	*/
#define UIC_EXT3	0x00000002	/* External  interrupt 3	*/
#define UIC_EXT4	0x00000001	/* External  interrupt 4	*/

#elif defined(CONFIG_405EX)

/* UIC 0 */
#define UIC_U0			0x80000000	/* */
#define UIC_U1			0x40000000	/* */
#define UIC_IIC0		0x20000000	/* */
#define UIC_PKA			0x10000000	/* */
#define UIC_TRNG		0x08000000	/* */
#define UIC_EBM			0x04000000	/* */
#define UIC_BGI			0x02000000	/* */
#define UIC_IIC1		0x01000000	/* */
#define UIC_SPI			0x00800000	/* */
#define UIC_EIRQ0		0x00400000	/**/
#define UIC_MTE			0x00200000	/*MAL Tx EOB */
#define UIC_MRE			0x00100000	/*MAL Rx EOB */
#define UIC_DMA0		0x00080000	/* */
#define UIC_DMA1		0x00040000	/* */
#define UIC_DMA2		0x00020000	/* */
#define UIC_DMA3		0x00010000	/* */
#define UIC_PCIE0AL		0x00008000	/* */
#define UIC_PCIE0VPD		0x00004000	/* */
#define UIC_RPCIE0HRST		0x00002000	/* */
#define UIC_FPCIE0HRST		0x00001000	/* */
#define UIC_PCIE0TCR		0x00000800	/* */
#define UIC_PCIEMSI0		0x00000400	/* */
#define UIC_PCIEMSI1		0x00000200	/* */
#define UIC_SECURITY		0x00000100	/* */
#define UIC_ENET		0x00000080	/* */
#define UIC_ENET1		0x00000040	/* */
#define UIC_PCIEMSI2		0x00000020	/* */
#define UIC_EIRQ4		0x00000010	/**/
#define UICB0_UIC2NCI		0x00000008	/* */
#define UICB0_UIC2CI		0x00000004	/* */
#define UICB0_UIC1NCI		0x00000002	/* */
#define UICB0_UIC1CI		0x00000001	/* */

#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
				 UICB0_UIC1CI | UICB0_UIC2NCI)

#define UIC_MAL_TXEOB		UIC_MTE/* MAL TXEOB			     */
#define UIC_MAL_RXEOB		UIC_MRE/* MAL RXEOB			     */
/* UIC 1 */
#define UIC_MS			0x80000000	/* MAL SERR */
#define UIC_MTDE		0x40000000	/* MAL TXDE */
#define UIC_MRDE		0x20000000	/* MAL RXDE */
#define UIC_PCIE0BMVC0		0x10000000	/* */
#define UIC_PCIE0DCRERR		0x08000000	/* */
#define UIC_EBC			0x04000000	/* */
#define UIC_NDFC		0x02000000	/* */
#define UIC_PCEI1DCRERR		0x01000000	/* */