m5227x.h

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#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
#define GPIO_PAR_TIMER_T3IN_SSIMCLK	(0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
#define GPIO_PAR_TIMER_T2IN_DSPIPCS2	(0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST	(0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
#define GPIO_PAR_TIMER_T0IN_LCDREV	(0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)

/* Bit definitions and macros for GPIO_PAR_LCDCTL */
#define GPIO_PAR_LCDCTL_ACDOE_MASK	(0xE7)
#define GPIO_PAR_LCDCTL_ACDOE_ACDOE	(0x18)
#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR	(0x10)
#define GPIO_PAR_LCDCTL_ACDOE_GPIO	(0x00)
#define GPIO_PAR_LCDCTL_FLM_VSYNC	(0x04)
#define GPIO_PAR_LCDCTL_LP_HSYNC	(0x02)
#define GPIO_PAR_LCDCTL_LSCLK		(0x01)

/* Bit definitions and macros for PAR_IRQ */
#define GPIO_PAR_IRQ_IRQ4_MASK		(0xF3)
#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK	(0x0C)
#define GPIO_PAR_IRQ_IRQ4_DMAREQ0	(0x08)
#define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
#define GPIO_PAR_IRQ_IRQ1_MASK		(0xFC)
#define GPIO_PAR_IRQ_IRQ1_PCIINT	(0x03)
#define GPIO_PAR_IRQ_IRQ1_USBCLKIN	(0x02)
#define GPIO_PAR_IRQ_IRQ1_SSICLKIN	(0x01)
#define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)

/* Bit definitions and macros for GPIO_PAR_LCDH */
#define GPIO_PAR_LCDH_LD17_MASK		(0xFFFFF3FF)
#define GPIO_PAR_LCDH_LD17_LD17		(0x00000C00)
#define GPIO_PAR_LCDH_LD17_LD11		(0x00000800)
#define GPIO_PAR_LCDH_LD17_GPIO		(0x00000000)

#define GPIO_PAR_LCDH_LD16_MASK		(0xFFFFFCFF)
#define GPIO_PAR_LCDH_LD16_LD16		(0x00000300)
#define GPIO_PAR_LCDH_LD16_LD10		(0x00000200)
#define GPIO_PAR_LCDH_LD16_GPIO		(0x00000000)

#define GPIO_PAR_LCDH_LD15_MASK		(0xFFFFFF3F)
#define GPIO_PAR_LCDH_LD15_LD15		(0x000000C0)
#define GPIO_PAR_LCDH_LD15_LD9		(0x00000080)
#define GPIO_PAR_LCDH_LD15_GPIO		(0x00000000)

#define GPIO_PAR_LCDH_LD14_MASK		(0xFFFFFFCF)
#define GPIO_PAR_LCDH_LD14_LD14		(0x00000030)
#define GPIO_PAR_LCDH_LD14_LD8		(0x00000020)
#define GPIO_PAR_LCDH_LD14_GPIO		(0x00000000)

#define GPIO_PAR_LCDH_LD13_MASK		(0xFFFFFFF3)
#define GPIO_PAR_LCDH_LD13_LD13		(0x0000000C)
#define GPIO_PAR_LCDH_LD13_CANTX	(0x00000008)
#define GPIO_PAR_LCDH_LD13_GPIO		(0x00000000)

#define GPIO_PAR_LCDH_LD12_MASK		(0xFFFFFFFC)
#define GPIO_PAR_LCDH_LD12_LD12		(0x00000003)
#define GPIO_PAR_LCDH_LD12_CANRX	(0x00000002)
#define GPIO_PAR_LCDH_LD12_GPIO		(0x00000000)

/* Bit definitions and macros for GPIO_PAR_LCDL */
#define GPIO_PAR_LCDL_LD11_MASK		(0x3FFFFFFF)
#define GPIO_PAR_LCDL_LD11_LD11		(0xC0000000)
#define GPIO_PAR_LCDL_LD11_LD7		(0x80000000)
#define GPIO_PAR_LCDL_LD11_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD10_MASK		(0xCFFFFFFF)
#define GPIO_PAR_LCDL_LD10_LD10		(0x30000000)
#define GPIO_PAR_LCDL_LD10_LD6		(0x20000000)
#define GPIO_PAR_LCDL_LD10_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD9_MASK		(0xF3FFFFFF)
#define GPIO_PAR_LCDL_LD9_LD9		(0x0C000000)
#define GPIO_PAR_LCDL_LD9_LD5		(0x08000000)
#define GPIO_PAR_LCDL_LD9_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD8_MASK		(0xFCFFFFFF)
#define GPIO_PAR_LCDL_LD8_LD8		(0x03000000)
#define GPIO_PAR_LCDL_LD8_LD4		(0x02000000)
#define GPIO_PAR_LCDL_LD8_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD7_MASK		(0xFF3FFFFF)
#define GPIO_PAR_LCDL_LD7_LD7		(0x00C00000)
#define GPIO_PAR_LCDL_LD7_PWM7		(0x00800000)
#define GPIO_PAR_LCDL_LD7_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD6_MASK		(0xFFCFFFFF)
#define GPIO_PAR_LCDL_LD6_LD6		(0x00300000)
#define GPIO_PAR_LCDL_LD6_PWM5		(0x00200000)
#define GPIO_PAR_LCDL_LD6_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD5_MASK		(0xFFF3FFFF)
#define GPIO_PAR_LCDL_LD5_LD5		(0x000C0000)
#define GPIO_PAR_LCDL_LD5_LD3		(0x00080000)
#define GPIO_PAR_LCDL_LD5_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD4_MASK		(0xFFFCFFFF)
#define GPIO_PAR_LCDL_LD4_LD4		(0x00030000)
#define GPIO_PAR_LCDL_LD4_LD2		(0x00020000)
#define GPIO_PAR_LCDL_LD4_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD3_MASK		(0xFFFF3FFF)
#define GPIO_PAR_LCDL_LD3_LD3		(0x0000C000)
#define GPIO_PAR_LCDL_LD3_LD1		(0x00008000)
#define GPIO_PAR_LCDL_LD3_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD2_MASK		(0xFFFFCFFF)
#define GPIO_PAR_LCDL_LD2_LD2		(0x00003000)
#define GPIO_PAR_LCDL_LD2_LD0		(0x00002000)
#define GPIO_PAR_LCDL_LD2_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD1_MASK		(0xFFFFF3FF)
#define GPIO_PAR_LCDL_LD1_LD1		(0x00000C00)
#define GPIO_PAR_LCDL_LD1_PWM3		(0x00000800)
#define GPIO_PAR_LCDL_LD1_GPIO		(0x00000000)

#define GPIO_PAR_LCDL_LD0_MASK		(0xFFFFFCFF)
#define GPIO_PAR_LCDL_LD0_LD0		(0x00000300)
#define GPIO_PAR_LCDL_LD0_PWM1		(0x00000200)
#define GPIO_PAR_LCDL_LD0_GPIO		(0x00000000)

/* Bit definitions and macros for MSCR_FB */
#define GPIO_MSCR_FB_DUPPER_MASK	(0xCF)
#define GPIO_MSCR_FB_DUPPER_25V_33V	(0x30)
#define GPIO_MSCR_FB_DUPPER_FULL_18V	(0x20)
#define GPIO_MSCR_FB_DUPPER_OD		(0x10)
#define GPIO_MSCR_FB_DUPPER_HALF_18V	(0x00)

#define GPIO_MSCR_FB_DLOWER_MASK	(0xF3)
#define GPIO_MSCR_FB_DLOWER_25V_33V	(0x0C)
#define GPIO_MSCR_FB_DLOWER_FULL_18V	(0x08)
#define GPIO_MSCR_FB_DLOWER_OD		(0x04)
#define GPIO_MSCR_FB_DLOWER_HALF_18V	(0x00)

#define GPIO_MSCR_FB_ADDRCTL_MASK	(0xFC)
#define GPIO_MSCR_FB_ADDRCTL_25V_33V	(0x03)
#define GPIO_MSCR_FB_ADDRCTL_FULL_18V	(0x02)
#define GPIO_MSCR_FB_ADDRCTL_OD		(0x01)
#define GPIO_MSCR_FB_ADDRCTL_HALF_18V	(0x00)

/* Bit definitions and macros for MSCR_SDRAM */
#define GPIO_MSCR_SDRAM_SDCLKB_MASK	(0xCF)
#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V	(0x30)
#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V	(0x20)
#define GPIO_MSCR_SDRAM_SDCLKB_OD	(0x10)
#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V	(0x00)

#define GPIO_MSCR_SDRAM_SDCLK_MASK	(0xF3)
#define GPIO_MSCR_SDRAM_SDCLK_25V_33V	(0x0C)
#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V	(0x08)
#define GPIO_MSCR_SDRAM_SDCLK_OPD	(0x04)
#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V	(0x00)

#define GPIO_MSCR_SDRAM_SDCTL_MASK	(0xFC)
#define GPIO_MSCR_SDRAM_SDCTL_25V_33V	(0x03)
#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V	(0x02)
#define GPIO_MSCR_SDRAM_SDCTL_OPD	(0x01)
#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V	(0x00)

/* Bit definitions and macros for Drive Strength Control */
#define DSCR_LOAD_50PF	(0x03)
#define DSCR_LOAD_30PF	(0x02)
#define DSCR_LOAD_20PF	(0x01)
#define DSCR_LOAD_10PF	(0x00)

/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/

/* Bit definitions and macros for SDMR */
#define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */
#define SDRAMC_SDMR_CMD			(0x00010000)	/* Command */
#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */
#define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */
#define SDRAMC_SDMR_BK_LMR		(0x00000000)
#define SDRAMC_SDMR_BK_LEMR		(0x40000000)

/* Bit definitions and macros for SDCR */
#define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
#define SDRAMC_SDCR_IPALL		(0x00000002)	/* Initiate Precharge All */
#define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */
#define SDRAMC_SDCR_MEM_PS		(0x00002000)	/* Data Port Size */
#define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
#define SDRAMC_SDCR_OE_RULE		(0x00400000)	/* Drive Rule Selection */
#define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */
#define SDRAMC_SDCR_DDR2_MODE		(0x08000000)	/* DDR2 Mode Select */
#define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
#define SDRAMC_SDCR_DDR_MODE		(0x20000000)	/* DDR Mode Select */
#define SDRAMC_SDCR_CKE			(0x40000000)	/* Clock Enable */
#define SDRAMC_SDCR_MODE_EN		(0x80000000)	/* SDRAM Mode Register Programming Enable */
#define SDRAMC_SDCR_DQS_OE_BOTH		(0x00000C000)

/* Bit definitions and macros for SDCFG1 */
#define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */
#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */
#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */
#define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */
#define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge delay */
#define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge delay */

/* Bit definitions and macros for SDCFG2 */
#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */
#define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */
#define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge delay */
#define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */

/* Bit definitions and macros for SDCS group */
#define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
#define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
#define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
#define SDRAMC_SDCS_CSSZ_DISABLE	(0x00000000)
#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)

/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/

/* Bit definitions and macros for PCR */
#define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
#define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for bus/flexbus clock frequency */
#define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for SDRAM clock frequency */
#define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
#define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
#define PLL_PCR_PFDR_MASK		(0x000F0000)
#define PLL_PCR_OUTDIV5_MASK		(0x000F0000)
#define PLL_PCR_OUTDIV3_MASK		(0x00000F00)
#define PLL_PCR_OUTDIV2_MASK		(0x000000F0)
#define PLL_PCR_OUTDIV1_MASK		(0x0000000F)

/* Bit definitions and macros for PSR */
#define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
#define PLL_PSR_LOCK			(0x00000002)	/* PLL lock status */
#define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
#define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */

/********************************************************************/

#endif				/* __MCF5227X__ */