📄 m5227x.h

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#define INTC_INTFRCH_INTFRC61		(0x20000000)#define INTC_INTFRCH_INTFRC62		(0x40000000)#define INTC_INTFRCH_INTFRC63		(0x80000000)/* Bit definitions and macros for INTFRCL */#define INTC_INTFRCL_INTFRC0		(0x00000001)#define INTC_INTFRCL_INTFRC1		(0x00000002)#define INTC_INTFRCL_INTFRC2		(0x00000004)#define INTC_INTFRCL_INTFRC3		(0x00000008)#define INTC_INTFRCL_INTFRC4		(0x00000010)#define INTC_INTFRCL_INTFRC5		(0x00000020)#define INTC_INTFRCL_INTFRC6		(0x00000040)#define INTC_INTFRCL_INTFRC7		(0x00000080)#define INTC_INTFRCL_INTFRC8		(0x00000100)#define INTC_INTFRCL_INTFRC9		(0x00000200)#define INTC_INTFRCL_INTFRC10		(0x00000400)#define INTC_INTFRCL_INTFRC11		(0x00000800)#define INTC_INTFRCL_INTFRC12		(0x00001000)#define INTC_INTFRCL_INTFRC13		(0x00002000)#define INTC_INTFRCL_INTFRC14		(0x00004000)#define INTC_INTFRCL_INTFRC15		(0x00008000)#define INTC_INTFRCL_INTFRC16		(0x00010000)#define INTC_INTFRCL_INTFRC17		(0x00020000)#define INTC_INTFRCL_INTFRC18		(0x00040000)#define INTC_INTFRCL_INTFRC19		(0x00080000)#define INTC_INTFRCL_INTFRC20		(0x00100000)#define INTC_INTFRCL_INTFRC21		(0x00200000)#define INTC_INTFRCL_INTFRC22		(0x00400000)#define INTC_INTFRCL_INTFRC23		(0x00800000)#define INTC_INTFRCL_INTFRC24		(0x01000000)#define INTC_INTFRCL_INTFRC25		(0x02000000)#define INTC_INTFRCL_INTFRC26		(0x04000000)#define INTC_INTFRCL_INTFRC27		(0x08000000)#define INTC_INTFRCL_INTFRC28		(0x10000000)#define INTC_INTFRCL_INTFRC29		(0x20000000)#define INTC_INTFRCL_INTFRC30		(0x40000000)#define INTC_INTFRCL_INTFRC31		(0x80000000)/* Bit definitions and macros for ICONFIG */#define INTC_ICONFIG_EMASK		(0x0020)#define INTC_ICONFIG_ELVLPRI1		(0x0200)#define INTC_ICONFIG_ELVLPRI2		(0x0400)#define INTC_ICONFIG_ELVLPRI3		(0x0800)#define INTC_ICONFIG_ELVLPRI4		(0x1000)#define INTC_ICONFIG_ELVLPRI5		(0x2000)#define INTC_ICONFIG_ELVLPRI6		(0x4000)#define INTC_ICONFIG_ELVLPRI7		(0x8000)/* Bit definitions and macros for SIMR */#define INTC_SIMR_SIMR(x)		(((x)&0x7F))/* Bit definitions and macros for CIMR */#define INTC_CIMR_CIMR(x)		(((x)&0x7F))/* Bit definitions and macros for CLMASK */#define INTC_CLMASK_CLMASK(x)		(((x)&0x0F))/* Bit definitions and macros for SLMASK */#define INTC_SLMASK_SLMASK(x)		(((x)&0x0F))/* Bit definitions and macros for ICR group */#define INTC_ICR_IL(x)			(((x)&0x07))/********************************************************************** Reset Controller Module (RCM)*********************************************************************//* Bit definitions and macros for RCR */#define RCM_RCR_FRCRSTOUT		(0x40)#define RCM_RCR_SOFTRST			(0x80)/* Bit definitions and macros for RSR */#define RCM_RSR_LOL			(0x01)#define RCM_RSR_WDR_CORE		(0x02)#define RCM_RSR_EXT			(0x04)#define RCM_RSR_POR			(0x08)#define RCM_RSR_SOFT			(0x20)/********************************************************************** Chip Configuration Module (CCM)*********************************************************************//* Bit definitions and macros for CCR */#define CCM_CCR_DRAMSEL			(0x0100)#define CCM_CCR_CSC_MASK		(0xFF3F)#define CCM_CCR_CSC_FBCS5_CS4		(0x00C0)#define CCM_CCR_CSC_FBCS5_A22		(0x0080)#define CCM_CCR_CSC_FB_A23_A22		(0x0040)#define CCM_CCR_LIMP			(0x0020)#define CCM_CCR_LOAD			(0x0010)#define CCM_CCR_BOOTPS_MASK		(0xFFF3)#define CCM_CCR_BOOTPS_PS16		(0x0008)#define CCM_CCR_BOOTPS_PS8		(0x0004)#define CCM_CCR_BOOTPS_PS32		(0x0000)#define CCM_CCR_OSCMODE_OSCBYPASS	(0x0002)/* Bit definitions and macros for RCON */#define CCM_RCON_CSC_MASK		(0xFF3F)#define CCM_RCON_CSC_FBCS5_CS4		(0x00C0)#define CCM_RCON_CSC_FBCS5_A22		(0x0080)#define CCM_RCON_CSC_FB_A23_A22		(0x0040)#define CCM_RCON_LIMP			(0x0020)#define CCM_RCON_LOAD			(0x0010)#define CCM_RCON_BOOTPS_MASK		(0xFFF3)#define CCM_RCON_BOOTPS_PS16		(0x0008)#define CCM_RCON_BOOTPS_PS8		(0x0004)#define CCM_RCON_BOOTPS_PS32		(0x0000)#define CCM_RCON_OSCMODE_OSCBYPASS	(0x0002)/* Bit definitions and macros for CIR */#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */#define CCM_CIR_PIN_MASK		(0xFFC0)#define CCM_CIR_PRN_MASK		(0x003F)#define CCM_CIR_PIN_MCF52277		(0x0000)/* Bit definitions and macros for MISCCR */#define CCM_MISCCR_RTCSRC		(0x4000)#define CCM_MISCCR_USBPUE		(0x2000)	/* USB transceiver pull-up */#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor ext en bit */#define CCM_MISCCR_BMT_65536		(0)#define CCM_MISCCR_BMT_32768		(1)#define CCM_MISCCR_BMT_16384		(2)#define CCM_MISCCR_BMT_8192		(3)#define CCM_MISCCR_BMT_4096		(4)#define CCM_MISCCR_BMT_2048		(5)#define CCM_MISCCR_BMT_1024		(6)#define CCM_MISCCR_BMT_512		(7)#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */#define CCM_MISCCR_LCDCHEN		(0x0004)	/* LCD Int CLK en */#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense pol */#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source *//* Bit definitions and macros for CDR */#define CCM_CDR_USBDIV(x)		(((x)&0x0003)<<12)#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clk div */#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clk div *//* Bit definitions and macros for UOCSR */#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (rd-only) */#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (rd-only) */#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (rd-only) */#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor en (rd-only) */#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (rd-only) */#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */#define CCM_UOCSR_SEND			(0x0010)	/* Session end */#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt en */#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down en *//********************************************************************** General Purpose I/O Module (GPIO)*********************************************************************//* Bit definitions and macros for PAR_BE */#define GPIO_PAR_BE_MASK		(0x0F)#define GPIO_PAR_BE_BE3_BE3		(0x08)#define GPIO_PAR_BE_BE3_GPIO		(0x00)#define GPIO_PAR_BE_BE2_BE2		(0x04)#define GPIO_PAR_BE_BE2_GPIO		(0x00)#define GPIO_PAR_BE_BE1_BE1		(0x02)#define GPIO_PAR_BE_BE1_GPIO		(0x00)#define GPIO_PAR_BE_BE0_BE0		(0x01)#define GPIO_PAR_BE_BE0_GPIO		(0x00)/* Bit definitions and macros for PAR_CS */#define GPIO_PAR_CS_CS3			(0x10)#define GPIO_PAR_CS_CS2			(0x08)#define GPIO_PAR_CS_CS1_FBCS1		(0x06)#define GPIO_PAR_CS_CS1_SDCS1		(0x04)#define GPIO_PAR_CS_CS1_GPIO		(0x00)#define GPIO_PAR_CS_CS0			(0x01)/* Bit definitions and macros for PAR_FBCTL */#define GPIO_PAR_FBCTL_OE		(0x80)#define GPIO_PAR_FBCTL_TA		(0x40)#define GPIO_PAR_FBCTL_RW		(0x20)#define GPIO_PAR_FBCTL_TS_MASK		(0xE7)#define GPIO_PAR_FBCTL_TS_FBTS		(0x18)#define GPIO_PAR_FBCTL_TS_DMAACK	(0x10)#define GPIO_PAR_FBCTL_TS_GPIO		(0x00)/* Bit definitions and macros for PAR_FECI2C */#define GPIO_PAR_I2C_SCL_MASK		(0xF3)#define GPIO_PAR_I2C_SCL_SCL		(0x0C)#define GPIO_PAR_I2C_SCL_CANTXD		(0x08)#define GPIO_PAR_I2C_SCL_U2TXD		(0x04)#define GPIO_PAR_I2C_SCL_GPIO		(0x00)#define GPIO_PAR_I2C_SDA_MASK		(0xFC)#define GPIO_PAR_I2C_SDA_SDA		(0x03)#define GPIO_PAR_I2C_SDA_CANRXD		(0x02)#define GPIO_PAR_I2C_SDA_U2RXD		(0x01)#define GPIO_PAR_I2C_SDA_GPIO		(0x00)/* Bit definitions and macros for PAR_UART */#define GPIO_PAR_UART_U1CTS_MASK	(0x3FFF)#define GPIO_PAR_UART_U1CTS_U1CTS	(0xC000)#define GPIO_PAR_UART_U1CTS_SSIBCLK	(0x8000)#define GPIO_PAR_UART_U1CTS_LCDCLS	(0x4000)#define GPIO_PAR_UART_U1CTS_GPIO	(0x0000)#define GPIO_PAR_UART_U1RTS_MASK	(0xCFFF)#define GPIO_PAR_UART_U1RTS_U1RTS	(0x3000)#define GPIO_PAR_UART_U1RTS_SSIFS	(0x2000)#define GPIO_PAR_UART_U1RTS_LCDPS	(0x1000)#define GPIO_PAR_UART_U1RTS_GPIO	(0x0000)#define GPIO_PAR_UART_U1RXD_MASK	(0xF3FF)#define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)#define GPIO_PAR_UART_U1RXD_SSIRXD	(0x0800)#define GPIO_PAR_UART_U1RXD_GPIO	(0x0000)#define GPIO_PAR_UART_U1TXD_MASK	(0xFCFF)#define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)#define GPIO_PAR_UART_U1TXD_SSITXD	(0x0200)#define GPIO_PAR_UART_U1TXD_GPIO	(0x0000)#define GPIO_PAR_UART_U0CTS_MASK	(0xFF3F)#define GPIO_PAR_UART_U0CTS_U0CTS	(0x00C0)#define GPIO_PAR_UART_U0CTS_T1OUT	(0x0080)#define GPIO_PAR_UART_U0CTS_USBVBUSEN	(0x0040)#define GPIO_PAR_UART_U0CTS_GPIO	(0x0000)#define GPIO_PAR_UART_U0RTS_MASK	(0xFFCF)#define GPIO_PAR_UART_U0RTS_U0RTS	(0x0030)#define GPIO_PAR_UART_U0RTS_T1IN	(0x0020)#define GPIO_PAR_UART_U0RTS_USBVBUSOC	(0x0010)#define GPIO_PAR_UART_U0RTS_GPIO	(0x0000)#define GPIO_PAR_UART_U0RXD_MASK	(0xFFF3)#define GPIO_PAR_UART_U0RXD_U0RXD	(0x000C)#define GPIO_PAR_UART_U0RXD_CANRX	(0x0008)#define GPIO_PAR_UART_U0RXD_GPIO	(0x0000)#define GPIO_PAR_UART_U0TXD_MASK	(0xFFFC)#define GPIO_PAR_UART_U0TXD_U0TXD	(0x0003)#define GPIO_PAR_UART_U0TXD_CANTX	(0x0002)#define GPIO_PAR_UART_U0TXD_GPIO	(0x0000)/* Bit definitions and macros for PAR_DSPI */#define GPIO_PAR_DSPI_PCS0_MASK		(0x3F)#define GPIO_PAR_DSPI_PCS0_PCS0		(0x80)#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x40)#define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)#define GPIO_PAR_DSPI_SIN_MASK		(0xCF)#define GPIO_PAR_DSPI_SIN_SIN		(0x30)#define GPIO_PAR_DSPI_SIN_U2RXD		(0x20)#define GPIO_PAR_DSPI_SIN_GPIO		(0x00)#define GPIO_PAR_DSPI_SOUT_MASK		(0xF3)#define GPIO_PAR_DSPI_SOUT_SOUT		(0x0C)#define GPIO_PAR_DSPI_SOUT_U2TXD	(0x08)#define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)#define GPIO_PAR_DSPI_SCK_MASK		(0xFC)#define GPIO_PAR_DSPI_SCK_SCK		(0x03)#define GPIO_PAR_DSPI_SCK_U2CTS		(0x02)#define GPIO_PAR_DSPI_SCK_GPIO		(0x00)/* Bit definitions and macros for PAR_TIMER */
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