📄 m5227x.h

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/* * MCF5227x Internal Memory Map * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __MCF5227X__#define __MCF5227X__/********************************************************************** Interrupt Controller (INTC)*********************************************************************/#define INT0_LO_RSVD0			(0)#define INT0_LO_EPORT1			(1)#define INT0_LO_EPORT4			(4)#define INT0_LO_EPORT7			(7)#define INT0_LO_EDMA_00			(8)#define INT0_LO_EDMA_01			(9)#define INT0_LO_EDMA_02			(10)#define INT0_LO_EDMA_03			(11)#define INT0_LO_EDMA_04			(12)#define INT0_LO_EDMA_05			(13)#define INT0_LO_EDMA_06			(14)#define INT0_LO_EDMA_07			(15)#define INT0_LO_EDMA_08			(16)#define INT0_LO_EDMA_09			(17)#define INT0_LO_EDMA_10			(18)#define INT0_LO_EDMA_11			(19)#define INT0_LO_EDMA_12			(20)#define INT0_LO_EDMA_13			(21)#define INT0_LO_EDMA_14			(22)#define INT0_LO_EDMA_15			(23)#define INT0_LO_EDMA_ERR		(24)#define INT0_LO_SCM_CWIC		(25)#define INT0_LO_UART0			(26)#define INT0_LO_UART1			(27)#define INT0_LO_UART2			(28)#define INT0_LO_I2C			(30)#define INT0_LO_DSPI			(31)#define INT0_HI_DTMR0			(32)#define INT0_HI_DTMR1			(33)#define INT0_HI_DTMR2			(34)#define INT0_HI_DTMR3			(35)#define INT0_HI_SCMIR			(62)#define INT0_HI_RTC_ISR			(63)#define INT1_HI_CAN_BOFFINT		(1)#define INT1_HI_CAN_ERRINT		(3)#define INT1_HI_CAN_BUF0I		(4)#define INT1_HI_CAN_BUF1I		(5)#define INT1_HI_CAN_BUF2I		(6)#define INT1_HI_CAN_BUF3I		(7)#define INT1_HI_CAN_BUF4I		(8)#define INT1_HI_CAN_BUF5I		(9)#define INT1_HI_CAN_BUF6I		(10)#define INT1_HI_CAN_BUF7I		(11)#define INT1_HI_CAN_BUF8I		(12)#define INT1_HI_CAN_BUF9I		(13)#define INT1_HI_CAN_BUF10I		(14)#define INT1_HI_CAN_BUF11I		(15)#define INT1_HI_CAN_BUF12I		(16)#define INT1_HI_CAN_BUF13I		(17)#define INT1_HI_CAN_BUF14I		(18)#define INT1_HI_CAN_BUF15I		(19)#define INT1_HI_PIT0_PIF		(43)#define INT1_HI_PIT1_PIF		(44)#define INT1_HI_USBOTG_STS		(47)#define INT1_HI_SSI_ISR			(49)#define INT1_HI_PWM_INT			(50)#define INT1_HI_LCDC_ISR		(51)#define INT1_HI_CCM_UOCSR		(53)#define INT1_HI_DSPI_EOQF		(54)#define INT1_HI_DSPI_TFFF		(55)#define INT1_HI_DSPI_TCF		(56)#define INT1_HI_DSPI_TFUF		(57)#define INT1_HI_DSPI_RFDF		(58)#define INT1_HI_DSPI_RFOF		(59)#define INT1_HI_DSPI_RFOF_TFUF		(60)#define INT1_HI_TOUCH_ADC		(61)#define INT1_HI_PLL_LOCKS		(62)/* Bit definitions and macros for IPRH */#define INTC_IPRH_INT32			(0x00000001)#define INTC_IPRH_INT33			(0x00000002)#define INTC_IPRH_INT34			(0x00000004)#define INTC_IPRH_INT35			(0x00000008)#define INTC_IPRH_INT36			(0x00000010)#define INTC_IPRH_INT37			(0x00000020)#define INTC_IPRH_INT38			(0x00000040)#define INTC_IPRH_INT39			(0x00000080)#define INTC_IPRH_INT40			(0x00000100)#define INTC_IPRH_INT41			(0x00000200)#define INTC_IPRH_INT42			(0x00000400)#define INTC_IPRH_INT43			(0x00000800)#define INTC_IPRH_INT44			(0x00001000)#define INTC_IPRH_INT45			(0x00002000)#define INTC_IPRH_INT46			(0x00004000)#define INTC_IPRH_INT47			(0x00008000)#define INTC_IPRH_INT48			(0x00010000)#define INTC_IPRH_INT49			(0x00020000)#define INTC_IPRH_INT50			(0x00040000)#define INTC_IPRH_INT51			(0x00080000)#define INTC_IPRH_INT52			(0x00100000)#define INTC_IPRH_INT53			(0x00200000)#define INTC_IPRH_INT54			(0x00400000)#define INTC_IPRH_INT55			(0x00800000)#define INTC_IPRH_INT56			(0x01000000)#define INTC_IPRH_INT57			(0x02000000)#define INTC_IPRH_INT58			(0x04000000)#define INTC_IPRH_INT59			(0x08000000)#define INTC_IPRH_INT60			(0x10000000)#define INTC_IPRH_INT61			(0x20000000)#define INTC_IPRH_INT62			(0x40000000)#define INTC_IPRH_INT63			(0x80000000)/* Bit definitions and macros for IPRL */#define INTC_IPRL_INT0			(0x00000001)#define INTC_IPRL_INT1			(0x00000002)#define INTC_IPRL_INT2			(0x00000004)#define INTC_IPRL_INT3			(0x00000008)#define INTC_IPRL_INT4			(0x00000010)#define INTC_IPRL_INT5			(0x00000020)#define INTC_IPRL_INT6			(0x00000040)#define INTC_IPRL_INT7			(0x00000080)#define INTC_IPRL_INT8			(0x00000100)#define INTC_IPRL_INT9			(0x00000200)#define INTC_IPRL_INT10			(0x00000400)#define INTC_IPRL_INT11			(0x00000800)#define INTC_IPRL_INT12			(0x00001000)#define INTC_IPRL_INT13			(0x00002000)#define INTC_IPRL_INT14			(0x00004000)#define INTC_IPRL_INT15			(0x00008000)#define INTC_IPRL_INT16			(0x00010000)#define INTC_IPRL_INT17			(0x00020000)#define INTC_IPRL_INT18			(0x00040000)#define INTC_IPRL_INT19			(0x00080000)#define INTC_IPRL_INT20			(0x00100000)#define INTC_IPRL_INT21			(0x00200000)#define INTC_IPRL_INT22			(0x00400000)#define INTC_IPRL_INT23			(0x00800000)#define INTC_IPRL_INT24			(0x01000000)#define INTC_IPRL_INT25			(0x02000000)#define INTC_IPRL_INT26			(0x04000000)#define INTC_IPRL_INT27			(0x08000000)#define INTC_IPRL_INT28			(0x10000000)#define INTC_IPRL_INT29			(0x20000000)#define INTC_IPRL_INT30			(0x40000000)#define INTC_IPRL_INT31			(0x80000000)/* Bit definitions and macros for IMRH */#define INTC_IMRH_INT_MASK32		(0x00000001)#define INTC_IMRH_INT_MASK33		(0x00000002)#define INTC_IMRH_INT_MASK34		(0x00000004)#define INTC_IMRH_INT_MASK35		(0x00000008)#define INTC_IMRH_INT_MASK36		(0x00000010)#define INTC_IMRH_INT_MASK37		(0x00000020)#define INTC_IMRH_INT_MASK38		(0x00000040)#define INTC_IMRH_INT_MASK39		(0x00000080)#define INTC_IMRH_INT_MASK40		(0x00000100)#define INTC_IMRH_INT_MASK41		(0x00000200)#define INTC_IMRH_INT_MASK42		(0x00000400)#define INTC_IMRH_INT_MASK43		(0x00000800)#define INTC_IMRH_INT_MASK44		(0x00001000)#define INTC_IMRH_INT_MASK45		(0x00002000)#define INTC_IMRH_INT_MASK46		(0x00004000)#define INTC_IMRH_INT_MASK47		(0x00008000)#define INTC_IMRH_INT_MASK48		(0x00010000)#define INTC_IMRH_INT_MASK49		(0x00020000)#define INTC_IMRH_INT_MASK50		(0x00040000)#define INTC_IMRH_INT_MASK51		(0x00080000)#define INTC_IMRH_INT_MASK52		(0x00100000)#define INTC_IMRH_INT_MASK53		(0x00200000)#define INTC_IMRH_INT_MASK54		(0x00400000)#define INTC_IMRH_INT_MASK55		(0x00800000)#define INTC_IMRH_INT_MASK56		(0x01000000)#define INTC_IMRH_INT_MASK57		(0x02000000)#define INTC_IMRH_INT_MASK58		(0x04000000)#define INTC_IMRH_INT_MASK59		(0x08000000)#define INTC_IMRH_INT_MASK60		(0x10000000)#define INTC_IMRH_INT_MASK61		(0x20000000)#define INTC_IMRH_INT_MASK62		(0x40000000)#define INTC_IMRH_INT_MASK63		(0x80000000)/* Bit definitions and macros for IMRL */#define INTC_IMRL_INT_MASK0		(0x00000001)#define INTC_IMRL_INT_MASK1		(0x00000002)#define INTC_IMRL_INT_MASK2		(0x00000004)#define INTC_IMRL_INT_MASK3		(0x00000008)#define INTC_IMRL_INT_MASK4		(0x00000010)#define INTC_IMRL_INT_MASK5		(0x00000020)#define INTC_IMRL_INT_MASK6		(0x00000040)#define INTC_IMRL_INT_MASK7		(0x00000080)#define INTC_IMRL_INT_MASK8		(0x00000100)#define INTC_IMRL_INT_MASK9		(0x00000200)#define INTC_IMRL_INT_MASK10		(0x00000400)#define INTC_IMRL_INT_MASK11		(0x00000800)#define INTC_IMRL_INT_MASK12		(0x00001000)#define INTC_IMRL_INT_MASK13		(0x00002000)#define INTC_IMRL_INT_MASK14		(0x00004000)#define INTC_IMRL_INT_MASK15		(0x00008000)#define INTC_IMRL_INT_MASK16		(0x00010000)#define INTC_IMRL_INT_MASK17		(0x00020000)#define INTC_IMRL_INT_MASK18		(0x00040000)#define INTC_IMRL_INT_MASK19		(0x00080000)#define INTC_IMRL_INT_MASK20		(0x00100000)#define INTC_IMRL_INT_MASK21		(0x00200000)#define INTC_IMRL_INT_MASK22		(0x00400000)#define INTC_IMRL_INT_MASK23		(0x00800000)#define INTC_IMRL_INT_MASK24		(0x01000000)#define INTC_IMRL_INT_MASK25		(0x02000000)#define INTC_IMRL_INT_MASK26		(0x04000000)#define INTC_IMRL_INT_MASK27		(0x08000000)#define INTC_IMRL_INT_MASK28		(0x10000000)#define INTC_IMRL_INT_MASK29		(0x20000000)#define INTC_IMRL_INT_MASK30		(0x40000000)#define INTC_IMRL_INT_MASK31		(0x80000000)/* Bit definitions and macros for INTFRCH */#define INTC_INTFRCH_INTFRC32		(0x00000001)#define INTC_INTFRCH_INTFRC33		(0x00000002)#define INTC_INTFRCH_INTFRC34		(0x00000004)#define INTC_INTFRCH_INTFRC35		(0x00000008)#define INTC_INTFRCH_INTFRC36		(0x00000010)#define INTC_INTFRCH_INTFRC37		(0x00000020)#define INTC_INTFRCH_INTFRC38		(0x00000040)#define INTC_INTFRCH_INTFRC39		(0x00000080)#define INTC_INTFRCH_INTFRC40		(0x00000100)#define INTC_INTFRCH_INTFRC41		(0x00000200)#define INTC_INTFRCH_INTFRC42		(0x00000400)#define INTC_INTFRCH_INTFRC43		(0x00000800)#define INTC_INTFRCH_INTFRC44		(0x00001000)#define INTC_INTFRCH_INTFRC45		(0x00002000)#define INTC_INTFRCH_INTFRC46		(0x00004000)#define INTC_INTFRCH_INTFRC47		(0x00008000)#define INTC_INTFRCH_INTFRC48		(0x00010000)#define INTC_INTFRCH_INTFRC49		(0x00020000)#define INTC_INTFRCH_INTFRC50		(0x00040000)#define INTC_INTFRCH_INTFRC51		(0x00080000)#define INTC_INTFRCH_INTFRC52		(0x00100000)#define INTC_INTFRCH_INTFRC53		(0x00200000)#define INTC_INTFRCH_INTFRC54		(0x00400000)#define INTC_INTFRCH_INTFRC55		(0x00800000)#define INTC_INTFRCH_INTFRC56		(0x01000000)#define INTC_INTFRCH_INTFRC57		(0x02000000)#define INTC_INTFRCH_INTFRC58		(0x04000000)#define INTC_INTFRCH_INTFRC59		(0x08000000)#define INTC_INTFRCH_INTFRC60		(0x10000000)
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