📄 m5235.h
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#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)#define GPIO_PAR_UART_U1RTS_MASK (0x0030)#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)#define GPIO_PAR_UART_U0RXD (0x0008)#define GPIO_PAR_UART_U0TXD (0x0004)#define GPIO_PAR_UART_U0CTS (0x0002)#define GPIO_PAR_UART_U0RTS (0x0001)#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)#define GPIO_PAR_QSPI_CS1_MASK (0xC0)#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)#define GPIO_PAR_QSPI_CS0 (0x20)#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)#define GPIO_PAR_QSPI_DIN_MASK (0x18)#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)#define GPIO_PAR_QSPI_DOUT (0x04)#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)#define GPIO_PAR_QSPI_SCK_MASK (0x03)#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)#define GPIO_PAR_DT3IN_MASK (0xC000)#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)#define GPIO_PAR_DT3IN_U2CTS (0x8000)#define GPIO_PAR_DT3IN_DT3IN (0xC000)#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)#define GPIO_PAR_DT2IN_MASK (0x3000)#define GPIO_PAR_DT2IN_DT2OUT (0x1000)#define GPIO_PAR_DT2IN_DREQ2 (0x2000)#define GPIO_PAR_DT2IN_DT2IN (0x3000)#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)#define GPIO_PAR_DT1IN_MASK (0x0C00)#define GPIO_PAR_DT1IN_DT1OUT (0x0400)#define GPIO_PAR_DT1IN_DREQ1 (0x0800)#define GPIO_PAR_DT1IN_DT1IN (0x0C00)#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)#define GPIO_PAR_DT0IN_MASK (0x0300)#define GPIO_PAR_DT0IN_DREQ0 (0x0200)#define GPIO_PAR_DT0IN_DT0IN (0x0300)#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)#define GPIO_PAR_DT3OUT_MASK (0x00C0)#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)#define GPIO_PAR_DT3OUT_U2RTS (0x0080)#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)#define GPIO_PAR_DT2OUT_MASK (0x0030)#define GPIO_PAR_DT2OUT_DACK2 (0x0020)#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)#define GPIO_PAR_DT1OUT_MASK (0x000C)#define GPIO_PAR_DT1OUT_DACK1 (0x0008)#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)#define GPIO_PAR_DT0OUT(x) ((x)&0x03)#define GPIO_PAR_DT0OUT_MASK (0x0003)#define GPIO_PAR_DT0OUT_DACK0 (0x0002)#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)#define GPIO_PAR_ETPU_TCRCLK (0x04)#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)/* Bit definitions and macros for GPIO_DSCR */#define GPIO_DSCR_EIM_EIM1 (0x10)#define GPIO_DSCR_EIM_EIM0 (0x01)#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)#define GPIO_DSCR_FECI2C_FEC (0x10)#define GPIO_DSCR_FECI2C_I2C (0x01)#define GPIO_DSCR_UART_IRQ (0x40)#define GPIO_DSCR_UART_UART2 (0x10)#define GPIO_DSCR_UART_UART1 (0x04)#define GPIO_DSCR_UART_UART0 (0x01)#define GPIO_DSCR_QSPI_QSPI (0x01)#define GPIO_DSCR_TIMER (0x01)/********************************************************************** Chip Configuration Module (CCM)*********************************************************************//* Bit definitions and macros for CCM_RCR */#define CCM_RCR_SOFTRST (0x80)#define CCM_RCR_FRCRSTOUT (0x40)/* Bit definitions and macros for CCM_RSR */#define CCM_RSR_SOFT (0x20)#define CCM_RSR_WDR (0x10)#define CCM_RSR_POR (0x08)#define CCM_RSR_EXT (0x04)#define CCM_RSR_LOC (0x02)#define CCM_RSR_LOL (0x01)/* Bit definitions and macros for CCM_CCR */#define CCM_CCR_LOAD (0x8000)#define CCM_CCR_SZEN (0x0040)#define CCM_CCR_PSTEN (0x0020)#define CCM_CCR_BME (0x0008)#define CCM_CCR_BMT(x) ((x)&0x07)#define CCM_CCR_BMT_MASK (0x0007)#define CCM_CCR_BMT_64K (0x0000)#define CCM_CCR_BMT_32K (0x0001)#define CCM_CCR_BMT_16K (0x0002)#define CCM_CCR_BMT_8K (0x0003)#define CCM_CCR_BMT_4K (0x0004)#define CCM_CCR_BMT_2K (0x0005)#define CCM_CCR_BMT_1K (0x0006)#define CCM_CCR_BMT_512 (0x0007)/* Bit definitions and macros for CCM_RCON */#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)#define CCM_RCON_RLOAD (0x0020)#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)#define CCM_RCON_BOOTPS_MASK (0x0018)#define CCM_RCON_BOOTPS_32 (0x0018)#define CCM_RCON_BOOTPS_16 (0x0008)#define CCM_RCON_BOOTPS_8 (0x0010)#define CCM_RCON_MODE (0x0001)/* Bit definitions and macros for CCM_CIR */#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)#define CCM_CIR_PRN(x) ((x)&0x003F)/********************************************************************** PLL Clock Module*********************************************************************//* Bit definitions and macros for PLL_SYNCR */#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)#define PLL_SYNCR_MFD_MASK (0x07000000)#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)#define PLL_SYNCR_RFC_MASK (0x00380000)#define PLL_SYNCR_LOCEN (0x00040000)#define PLL_SYNCR_LOLRE (0x00020000)#define PLL_SYNCR_LOCRE (0x00010000)#define PLL_SYNCR_DISCLK (0x00008000)#define PLL_SYNCR_LOLIRQ (0x00004000)#define PLL_SYNCR_LOCIRQ (0x00002000)#define PLL_SYNCR_RATE (0x00001000)#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)#define PLL_SYNCR_EXP(x) ((x)&0x03FF)/* Bit definitions and macros for PLL_SYNSR */#define PLL_SYNSR_LOLF (0x00000200)#define PLL_SYNSR_LOC (0x00000100)#define PLL_SYNSR_MODE (0x00000080)#define PLL_SYNSR_PLLSEL (0x00000040)#define PLL_SYNSR_PLLREF (0x00000020)#define PLL_SYNSR_LOCKS (0x00000010)#define PLL_SYNSR_LOCK (0x00000008)#define PLL_SYNSR_LOCF (0x00000004)#define PLL_SYNSR_CALDONE (0x00000002)#define PLL_SYNSR_CALPASS (0x00000001)/********************************************************************* * Edge Port*********************************************************************/#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)#define EPORT_EPIER_EPIE7 (0x80)#define EPORT_EPIER_EPIE6 (0x40)#define EPORT_EPIER_EPIE5 (0x20)#define EPORT_EPIER_EPIE4 (0x10)#define EPORT_EPIER_EPIE3 (0x08)#define EPORT_EPIER_EPIE2 (0x04)#define EPORT_EPIER_EPIE1 (0x02)#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1/********************************************************************** Watchdog Timer Modules (WTM)*********************************************************************//* Bit definitions and macros for WTM_WCR */#define WTM_WCR_WAIT (0x0008)#define WTM_WCR_DOZE (0x0004)#define WTM_WCR_HALTED (0x0002)#define WTM_WCR_EN (0x0001)/********************************************************************** FlexCAN Module (CAN)*********************************************************************//* Bit definitions and macros for CAN_CANMCR */#define CANMCR_MDIS (0x80000000)#define CANMCR_FRZ (0x40000000)#define CANMCR_HALT (0x10000000)#define CANMCR_NORDY (0x08000000)#define CANMCR_SOFTRST (0x02000000)#define CANMCR_FRZACK (0x01000000)#define CANMCR_SUPV (0x00800000)#define CANMCR_LPMACK (0x00100000)#define CANMCR_MAXMB(x) (((x)&0x0F))/* Bit definitions and macros for CAN_CANCTRL */#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)#define CANCTRL_RJW(x) (((x)&0x03)<<22)#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)#define CANCTRL_BOFFMSK (0x00008000)#define CANCTRL_ERRMSK (0x00004000)#define CANCTRL_CLKSRC (0x00002000)#define CANCTRL_LPB (0x00001000)#define CANCTRL_SMP (0x00000080)#define CANCTRL_BOFFREC (0x00000040)#define CANCTRL_TSYNC (0x00000020)#define CANCTRL_LBUF (0x00000010)#define CANCTRL_LOM (0x00000008)#define CANCTRL_PROPSEG(x) (((x)&0x07))/* Bit definitions and macros for CAN_TIMER */#define TIMER_TIMER(x) ((x)&0xFFFF)/* Bit definitions and macros for CAN_RXGMASK */#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)/* Bit definitions and macros for CAN_ERRCNT */#define ERRCNT_TXECTR(x) (((x)&0xFF))#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)/* Bit definitions and macros for CAN_ERRSTAT */#define ERRSTAT_BITERR1 (0x00008000)#define ERRSTAT_BITERR0 (0x00004000)#define ERRSTAT_ACKERR (0x00002000)#define ERRSTAT_CRCERR (0x00001000)#define ERRSTAT_FRMERR (0x00000800)#define ERRSTAT_STFERR (0x00000400)#define ERRSTAT_TXWRN (0x00000200)#define ERRSTAT_RXWRN (0x00000100)#define ERRSTAT_IDLE (0x00000080)#define ERRSTAT_TXRX (0x00000040)#define ERRSTAT_FLT_BUSOFF (0x00000020)#define ERRSTAT_FLT_PASSIVE (0x00000010)#define ERRSTAT_FLT_ACTIVE (0x00000000)#define ERRSTAT_BOFFINT (0x00000004)#define ERRSTAT_ERRINT (0x00000002)/* Bit definitions and macros for CAN_IMASK */#define IMASK_BUF15M (0x00008000)#define IMASK_BUF14M (0x00004000)#define IMASK_BUF13M (0x00002000)#define IMASK_BUF12M (0x00001000)#define IMASK_BUF11M (0x00000800)#define IMASK_BUF10M (0x00000400)#define IMASK_BUF9M (0x00000200)#define IMASK_BUF8M (0x00000100)#define IMASK_BUF7M (0x00000080)#define IMASK_BUF6M (0x00000040)#define IMASK_BUF5M (0x00000020)#define IMASK_BUF4M (0x00000010)#define IMASK_BUF3M (0x00000008)#define IMASK_BUF2M (0x00000004)#define IMASK_BUF1M (0x00000002)#define IMASK_BUF0M (0x00000001)/* Bit definitions and macros for CAN_IFLAG */#define IFLAG_BUF15I (0x00008000)#define IFLAG_BUF14I (0x00004000)#define IFLAG_BUF13I (0x00002000)#define IFLAG_BUF12I (0x00001000)#define IFLAG_BUF11I (0x00000800)#define IFLAG_BUF10I (0x00000400)#define IFLAG_BUF9I (0x00000200)#define IFLAG_BUF8I (0x00000100)#define IFLAG_BUF7I (0x00000080)#define IFLAG_BUF6I (0x00000040)#define IFLAG_BUF5I (0x00000020)#define IFLAG_BUF4I (0x00000010)#define IFLAG_BUF3I (0x00000008)#define IFLAG_BUF2I (0x00000004)#define IFLAG_BUF1I (0x00000002)#define IFLAG_BUF0I (0x00000001)#endif /* mcf5235_h */⌨️ 快捷键说明
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