📄 m5235.h
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#define INT0_HI_CAN1_BUF4I (47)#define INT0_HI_CAN1_BUF5I (48)#define INT0_HI_CAN1_BUF6I (49)#define INT0_HI_CAN1_BUF7I (50)#define INT0_HI_CAN1_BUF8I (51)#define INT0_HI_CAN1_BUF9I (52)#define INT0_HI_CAN1_BUF10I (53)#define INT0_HI_CAN1_BUF11I (54)#define INT0_HI_CAN1_BUF12I (55)#define INT0_HI_CAN1_BUF13I (56)#define INT0_HI_CAN1_BUF14I (57)#define INT0_HI_CAN1_BUF15I (58)#define INT0_HI_CAN1_ERRINT (59)#define INT0_HI_CAN1_BOFFINT (60)/* 60-63 Reserved *//* 0 - 7 Reserved */#define INT1_LO_CAN1_BUF0I (8)#define INT1_LO_CAN1_BUF1I (9)#define INT1_LO_CAN1_BUF2I (10)#define INT1_LO_CAN1_BUF3I (11)#define INT1_LO_CAN1_BUF4I (12)#define INT1_LO_CAN1_BUF5I (13)#define INT1_LO_CAN1_BUF6I (14)#define INT1_LO_CAN1_BUF7I (15)#define INT1_LO_CAN1_BUF8I (16)#define INT1_LO_CAN1_BUF9I (17)#define INT1_LO_CAN1_BUF10I (18)#define INT1_LO_CAN1_BUF11I (19)#define INT1_LO_CAN1_BUF12I (20)#define INT1_LO_CAN1_BUF13I (21)#define INT1_LO_CAN1_BUF14I (22)#define INT1_LO_CAN1_BUF15I (23)#define INT1_LO_CAN1_ERRINT (24)#define INT1_LO_CAN1_BOFFINT (25)/* 26 Reserved */#define INT1_LO_ETPU_TC0F (27)#define INT1_LO_ETPU_TC1F (28)#define INT1_LO_ETPU_TC2F (29)#define INT1_LO_ETPU_TC3F (30)#define INT1_LO_ETPU_TC4F (31)#define INT1_HI_ETPU_TC5F (32)#define INT1_HI_ETPU_TC6F (33)#define INT1_HI_ETPU_TC7F (34)#define INT1_HI_ETPU_TC8F (35)#define INT1_HI_ETPU_TC9F (36)#define INT1_HI_ETPU_TC10F (37)#define INT1_HI_ETPU_TC11F (38)#define INT1_HI_ETPU_TC12F (39)#define INT1_HI_ETPU_TC13F (40)#define INT1_HI_ETPU_TC14F (41)#define INT1_HI_ETPU_TC15F (42)#define INT1_HI_ETPU_TC16F (43)#define INT1_HI_ETPU_TC17F (44)#define INT1_HI_ETPU_TC18F (45)#define INT1_HI_ETPU_TC19F (46)#define INT1_HI_ETPU_TC20F (47)#define INT1_HI_ETPU_TC21F (48)#define INT1_HI_ETPU_TC22F (49)#define INT1_HI_ETPU_TC23F (50)#define INT1_HI_ETPU_TC24F (51)#define INT1_HI_ETPU_TC25F (52)#define INT1_HI_ETPU_TC26F (53)#define INT1_HI_ETPU_TC27F (54)#define INT1_HI_ETPU_TC28F (55)#define INT1_HI_ETPU_TC29F (56)#define INT1_HI_ETPU_TC30F (57)#define INT1_HI_ETPU_TC31F (58)#define INT1_HI_ETPU_TGIF (59)/* Bit definitions and macros for INTC_IPRH */#define INTC_IPRH_INT63 (0x80000000)#define INTC_IPRH_INT62 (0x40000000)#define INTC_IPRH_INT61 (0x20000000)#define INTC_IPRH_INT60 (0x10000000)#define INTC_IPRH_INT59 (0x08000000)#define INTC_IPRH_INT58 (0x04000000)#define INTC_IPRH_INT57 (0x02000000)#define INTC_IPRH_INT56 (0x01000000)#define INTC_IPRH_INT55 (0x00800000)#define INTC_IPRH_INT54 (0x00400000)#define INTC_IPRH_INT53 (0x00200000)#define INTC_IPRH_INT52 (0x00100000)#define INTC_IPRH_INT51 (0x00080000)#define INTC_IPRH_INT50 (0x00040000)#define INTC_IPRH_INT49 (0x00020000)#define INTC_IPRH_INT48 (0x00010000)#define INTC_IPRH_INT47 (0x00008000)#define INTC_IPRH_INT46 (0x00004000)#define INTC_IPRH_INT45 (0x00002000)#define INTC_IPRH_INT44 (0x00001000)#define INTC_IPRH_INT43 (0x00000800)#define INTC_IPRH_INT42 (0x00000400)#define INTC_IPRH_INT41 (0x00000200)#define INTC_IPRH_INT40 (0x00000100)#define INTC_IPRH_INT39 (0x00000080)#define INTC_IPRH_INT38 (0x00000040)#define INTC_IPRH_INT37 (0x00000020)#define INTC_IPRH_INT36 (0x00000010)#define INTC_IPRH_INT35 (0x00000008)#define INTC_IPRH_INT34 (0x00000004)#define INTC_IPRH_INT33 (0x00000002)#define INTC_IPRH_INT32 (0x00000001)/* Bit definitions and macros for INTC_IPRL */#define INTC_IPRL_INT31 (0x80000000)#define INTC_IPRL_INT30 (0x40000000)#define INTC_IPRL_INT29 (0x20000000)#define INTC_IPRL_INT28 (0x10000000)#define INTC_IPRL_INT27 (0x08000000)#define INTC_IPRL_INT26 (0x04000000)#define INTC_IPRL_INT25 (0x02000000)#define INTC_IPRL_INT24 (0x01000000)#define INTC_IPRL_INT23 (0x00800000)#define INTC_IPRL_INT22 (0x00400000)#define INTC_IPRL_INT21 (0x00200000)#define INTC_IPRL_INT20 (0x00100000)#define INTC_IPRL_INT19 (0x00080000)#define INTC_IPRL_INT18 (0x00040000)#define INTC_IPRL_INT17 (0x00020000)#define INTC_IPRL_INT16 (0x00010000)#define INTC_IPRL_INT15 (0x00008000)#define INTC_IPRL_INT14 (0x00004000)#define INTC_IPRL_INT13 (0x00002000)#define INTC_IPRL_INT12 (0x00001000)#define INTC_IPRL_INT11 (0x00000800)#define INTC_IPRL_INT10 (0x00000400)#define INTC_IPRL_INT9 (0x00000200)#define INTC_IPRL_INT8 (0x00000100)#define INTC_IPRL_INT7 (0x00000080)#define INTC_IPRL_INT6 (0x00000040)#define INTC_IPRL_INT5 (0x00000020)#define INTC_IPRL_INT4 (0x00000010)#define INTC_IPRL_INT3 (0x00000008)#define INTC_IPRL_INT2 (0x00000004)#define INTC_IPRL_INT1 (0x00000002)#define INTC_IPRL_INT0 (0x00000001)/* Bit definitions and macros for INTC_IRLR */#define INTC_IRLRn(x) (((x)&0x7F)<<1)/* Bit definitions and macros for INTC_IACKLPRn */#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)/* Bit definitions and macros for INTC_ICRnx */#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)#define INTC_ICRnx_IP(x) ((x)&0x07)/********************************************************************** General Purpose I/O (GPIO)*********************************************************************//* Bit definitions and macros for GPIO_PODR */#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)#define GPIO_PODR_ADDR_MASK (0xE0)#define GPIO_PODR_BS(x) ((x)&0x0F)#define GPIO_PODR_BS_MASK (0x0F)#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)#define GPIO_PODR_CS_MASK (0xFE)#define GPIO_PODR_SDRAM(X) ((x)&0x3F)#define GPIO_PODR_SDRAM_MASK (0x3F)#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK#define GPIO_PODR_UARTH(x) ((x)&0x03)#define GPIO_PODR_UARTH_MASK (0x03)#define GPIO_PODR_QSPI(x) ((x)&0x1F)#define GPIO_PODR_QSPI_MASK (0x1F)#define GPIO_PODR_ETPU(x) ((x)&0x07)#define GPIO_PODR_ETPU_MASK (0x07)/* Bit definitions and macros for GPIO_PDDR */#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK/* Bit definitions and macros for GPIO_PPDSDR */#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK/* Bit definitions and macros for GPIO_PCLRR */#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK/* Bit definitions and macros for GPIO_PAR */#define GPIO_PAR_AD_ADDR23 (0x80)#define GPIO_PAR_AD_ADDR22 (0x40)#define GPIO_PAR_AD_ADDR21 (0x20)#define GPIO_PAR_AD_DATAL (0x01)#define GPIO_PAR_BUSCTL_OE (0x4000)#define GPIO_PAR_BUSCTL_TA (0x1000)#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)#define GPIO_PAR_BUSCTL_RWB (0x0100)#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)#define GPIO_PAR_BS(x) ((x)&0x0F)#define GPIO_PAR_BS_MASK (0x0F)#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)#define GPIO_PAR_CS_MASK (0xFE)#define GPIO_PAR_CS_CS7 (0x80)#define GPIO_PAR_CS_CS6 (0x40)#define GPIO_PAR_CS_CS5 (0x20)#define GPIO_PAR_CS_CS4 (0x10)#define GPIO_PAR_CS_CS3 (0x08)#define GPIO_PAR_CS_CS2 (0x04)#define GPIO_PAR_CS_CS1 (0x02)#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)#define GPIO_PAR_SDRAM_SDWE (0x20)#define GPIO_PAR_SDRAM_SCAS (0x10)#define GPIO_PAR_SDRAM_SRAS (0x08)#define GPIO_PAR_SDRAM_SCKE (0x04)#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)#define GPIO_PAR_FECI2C_SDA_MASK (0x03)#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)#define GPIO_PAR_UART_DREQ2 (0x8000)#define GPIO_PAR_UART_CAN1EN (0x4000)#define GPIO_PAR_UART_U2RXD (0x2000)#define GPIO_PAR_UART_U2TXD (0x1000)#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)#define GPIO_PAR_UART_U1TXD_MASK (0x0300)#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)⌨️ 快捷键说明
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