📄 m5235.h
字号:
/* * mcf5329.h -- Definitions for Freescale Coldfire 5329 * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef mcf5235_h#define mcf5235_h/****************************************************************************//********************************************************************** System Control Module (SCM)*********************************************************************//* Bit definition and macros for SCM_IPSBAR */#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)#define SCM_IPSBAR_V (0x00000001)/* Bit definition and macros for SCM_RAMBAR */#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)#define SCM_RAMBAR_BDE (0x00000200)/* Bit definition and macros for SCM_CRSR */#define SCM_CRSR_EXT (0x80)/* Bit definitions and macros for SCM_CWCR */#define SCM_CWCR_CWE (0x80)#define SCM_CWCR_CWRI (0x40)#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)#define SCM_CWCR_CWTA (0x04)#define SCM_CWCR_CWTAVAL (0x02)#define SCM_CWCR_CWTIC (0x01)/* Bit definitions and macros for SCM_LPICR */#define SCM_LPICR_ENBSTOP (0x80)#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)#define SCM_LPICR_XLPM_IPL_ANY (0x00)#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)#define SCM_LPICR_XLPM_IPL_L7 (0x70)/* Bit definitions and macros for SCM_DMAREQC */#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)#define SCM_DMAREQC_EXT_ETPU (0x00080000)#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))#define SCM_DMAREQC_DMACn_DTMR0 (0x04)#define SCM_DMAREQC_DMACn_DTMR1 (0x05)#define SCM_DMAREQC_DMACn_DTMR2 (0x06)#define SCM_DMAREQC_DMACn_DTMR3 (0x07)#define SCM_DMAREQC_DMACn_UART0RX (0x08)#define SCM_DMAREQC_DMACn_UART1RX (0x09)#define SCM_DMAREQC_DMACn_UART2RX (0x0A)#define SCM_DMAREQC_DMACn_UART0TX (0x0C)#define SCM_DMAREQC_DMACn_UART1TX (0x0D)#define SCM_DMAREQC_DMACn_UART3TX (0x0E)/* Bit definitions and macros for SCM_MPARK */#define SCM_MPARK_M2_P_EN (0x02000000)#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)#define SCM_MPARK_M3_PRTY_4TH (0x00000000)#define SCM_MPARK_M3_PRTY_3RD (0x00400000)#define SCM_MPARK_M3_PRTY_2ND (0x00800000)#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)#define SCM_MPARK_M2_PRTY_MSK (0x00300000)#define SCM_MPARK_M2_PRTY_4TH (0x00000000)#define SCM_MPARK_M2_PRTY_3RD (0x00100000)#define SCM_MPARK_M2_PRTY_2ND (0x00200000)#define SCM_MPARK_M2_PRTY_1ST (0x00300000)#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)#define SCM_MPARK_M0_PRTY_4TH (0x00000000)#define SCM_MPARK_M0_PRTY_3RD (0x00040000)#define SCM_MPARK_M0_PRTY_2ND (0x00080000)#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)#define SCM_MPARK_FIXED (0x00004000)#define SCM_MPARK_TIMEOUT (0x00002000)#define SCM_MPARK_PRKLAST (0x00001000)#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)/* Bit definitions and macros for SCM_MPR */#define SCM_MPR_MPR3 (0x08)#define SCM_MPR_MPR2 (0x04)#define SCM_MPR_MPR1 (0x02)#define SCM_MPR_MPR0 (0x01)/* Bit definitions and macros for SCM_PACRn */#define SCM_PACRn_LOCK1 (0x80)#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)#define SCM_PACRn_LOCK0 (0x08)#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))/* Bit definitions and macros for SCM_GPACR */#define SCM_PACRn_LOCK (0x80)#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))/********************************************************************** SDRAM Controller (SDRAMC)*********************************************************************//* Bit definitions and macros for SDRAMC_DCR */#define SDRAMC_DCR_NAM (0x2000)#define SDRAMC_DCR_COC (0x1000)#define SDRAMC_DCR_IS (0x0800)#define SDRAMC_DCR_RTIM_MASK (0x0C00)#define SDRAMC_DCR_RTIM_3CLKS (0x0000)#define SDRAMC_DCR_RTIM_6CLKS (0x0200)#define SDRAMC_DCR_RTIM_9CLKS (0x0400)#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)/* Bit definitions and macros for SDRAMC_DARCn */#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)#define SDRAMC_DARCn_RE (0x00008000)#define SDRAMC_DARCn_CASL_MASK (0x00003000)#define SDRAMC_DARCn_CASL_C0 (0x00000000)#define SDRAMC_DARCn_CASL_C1 (0x00001000)#define SDRAMC_DARCn_CASL_C2 (0x00002000)#define SDRAMC_DARCn_CASL_C3 (0x00003000)#define SDRAMC_DARCn_CBM_MASK (0x00000700)#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)#define SDRAMC_DARCn_IMRS (0x00000040)#define SDRAMC_DARCn_PS_MASK (0x00000030)#define SDRAMC_DARCn_PS_32 (0x00000000)#define SDRAMC_DARCn_PS_16 (0x00000010)#define SDRAMC_DARCn_PS_8 (0x00000020)#define SDRAMC_DARCn_IP (0x00000008)/* Bit definitions and macros for SDRAMC_DMRn */#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)#define SDRAMC_DMRn_WP (0x00000100)#define SDRAMC_DMRn_V (0x00000001)/********************************************************************** FlexBus Chip Selects (FBCS)*********************************************************************//* Bit definitions and macros for FBCS_CSMR */#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)#define FBCS_CSMR_BAM_4G (0xFFFF0000)#define FBCS_CSMR_BAM_2G (0x7FFF0000)#define FBCS_CSMR_BAM_1G (0x3FFF0000)#define FBCS_CSMR_BAM_1024M (0x3FFF0000)#define FBCS_CSMR_BAM_512M (0x1FFF0000)#define FBCS_CSMR_BAM_256M (0x0FFF0000)#define FBCS_CSMR_BAM_128M (0x07FF0000)#define FBCS_CSMR_BAM_64M (0x03FF0000)#define FBCS_CSMR_BAM_32M (0x01FF0000)#define FBCS_CSMR_BAM_16M (0x00FF0000)#define FBCS_CSMR_BAM_8M (0x007F0000)#define FBCS_CSMR_BAM_4M (0x003F0000)#define FBCS_CSMR_BAM_2M (0x001F0000)#define FBCS_CSMR_BAM_1M (0x000F0000)#define FBCS_CSMR_BAM_1024K (0x000F0000)#define FBCS_CSMR_BAM_512K (0x00070000)#define FBCS_CSMR_BAM_256K (0x00030000)#define FBCS_CSMR_BAM_128K (0x00010000)#define FBCS_CSMR_BAM_64K (0x00000000)#define FBCS_CSMR_WP (0x00000100)#define FBCS_CSMR_V (0x00000001)/* Bit definitions and macros for FBCS_CSCR */#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)#define FBCS_CSCR_AA (0x0100)#define FBCS_CSCR_PS_MASK (0x00C0)#define FBCS_CSCR_PS_32 (0x0000)#define FBCS_CSCR_PS_16 (0x0080)#define FBCS_CSCR_PS_8 (0x0040)#define FBCS_CSCR_BEM (0x0020)#define FBCS_CSCR_BSTR (0x0010)#define FBCS_CSCR_BSTW (0x0008)#define FBCS_CSCR_SWWS(x) ((x)&0x07)/********************************************************************** Queued Serial Peripheral Interface (QSPI)*********************************************************************//* Bit definitions and macros for QSPI_QMR */#define QSPI_QMR_MSTR (0x8000)#define QSPI_QMR_DOHIE (0x4000)#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)#define QSPI_QMR_CPOL (0x0200)#define QSPI_QMR_CPHA (0x0100)#define QSPI_QMR_BAUD(x) ((x)&0x00FF)/* Bit definitions and macros for QSPI_QDLYR */#define QSPI_QDLYR_SPE (0x8000)#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)/* Bit definitions and macros for QSPI_QWR */#define QSPI_QWR_HALT (0x8000)#define QSPI_QWR_WREN (0x4000)#define QSPI_QWR_WRTO (0x2000)#define QSPI_QWR_CSIV (0x1000)#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)#define QSPI_QWR_NEWQP(x) ((x)&0x000F)/* Bit definitions and macros for QSPI_QIR */#define QSPI_QIR_WCEFB (0x8000)#define QSPI_QIR_ABRTB (0x4000)#define QSPI_QIR_ABRTL (0x1000)#define QSPI_QIR_WCEFE (0x0800)#define QSPI_QIR_ABRTE (0x0400)#define QSPI_QIR_SPIFE (0x0100)#define QSPI_QIR_WCEF (0x0008)#define QSPI_QIR_ABRT (0x0004)#define QSPI_QIR_SPIF (0x0001)/* Bit definitions and macros for QSPI_QAR */#define QSPI_QAR_ADDR(x) ((x)&0x003F)/* Bit definitions and macros for QSPI_QDR */#define QSPI_QDR_CONT (0x8000)#define QSPI_QDR_BITSE (0x4000)#define QSPI_QDR_DT (0x2000)#define QSPI_QDR_DSCK (0x1000)#define QSPI_QDR_QSPI_CS3 (0x0800)#define QSPI_QDR_QSPI_CS2 (0x0400)#define QSPI_QDR_QSPI_CS1 (0x0200)#define QSPI_QDR_QSPI_CS0 (0x0100)/********************************************************************** Interrupt Controller (INTC)*********************************************************************/#define INT0_LO_RSVD0 (0)#define INT0_LO_EPORT1 (1)#define INT0_LO_EPORT2 (2)#define INT0_LO_EPORT3 (3)#define INT0_LO_EPORT4 (4)#define INT0_LO_EPORT5 (5)#define INT0_LO_EPORT6 (6)#define INT0_LO_EPORT7 (7)#define INT0_LO_SCM (8)#define INT0_LO_DMA0 (9)#define INT0_LO_DMA1 (10)#define INT0_LO_DMA2 (11)#define INT0_LO_DMA3 (12)#define INT0_LO_UART0 (13)#define INT0_LO_UART1 (14)#define INT0_LO_UART2 (15)#define INT0_LO_RSVD1 (16)#define INT0_LO_I2C (17)#define INT0_LO_QSPI (18)#define INT0_LO_DTMR0 (19)#define INT0_LO_DTMR1 (20)#define INT0_LO_DTMR2 (21)#define INT0_LO_DTMR3 (22)#define INT0_LO_FEC_TXF (23)#define INT0_LO_FEC_TXB (24)#define INT0_LO_FEC_UN (25)#define INT0_LO_FEC_RL (26)#define INT0_LO_FEC_RXF (27)#define INT0_LO_FEC_RXB (28)#define INT0_LO_FEC_MII (29)#define INT0_LO_FEC_LC (30)#define INT0_LO_FEC_HBERR (31)#define INT0_HI_FEC_GRA (32)#define INT0_HI_FEC_EBERR (33)#define INT0_HI_FEC_BABT (34)#define INT0_HI_FEC_BABR (35)#define INT0_HI_PIT0 (36)#define INT0_HI_PIT1 (37)#define INT0_HI_PIT2 (38)#define INT0_HI_PIT3 (39)#define INT0_HI_RNG (40)#define INT0_HI_SKHA (41)#define INT0_HI_MDHA (42)#define INT0_HI_CAN1_BUF0I (43)#define INT0_HI_CAN1_BUF1I (44)#define INT0_HI_CAN1_BUF2I (45)#define INT0_HI_CAN1_BUF3I (46)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -