📄 m5445x.h

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#define INTC_INTFRCL_INTFRC24		(0x01000000)#define INTC_INTFRCL_INTFRC25		(0x02000000)#define INTC_INTFRCL_INTFRC26		(0x04000000)#define INTC_INTFRCL_INTFRC27		(0x08000000)#define INTC_INTFRCL_INTFRC28		(0x10000000)#define INTC_INTFRCL_INTFRC29		(0x20000000)#define INTC_INTFRCL_INTFRC30		(0x40000000)#define INTC_INTFRCL_INTFRC31		(0x80000000)/* Bit definitions and macros for ICONFIG */#define INTC_ICONFIG_EMASK		(0x0020)#define INTC_ICONFIG_ELVLPRI1		(0x0200)#define INTC_ICONFIG_ELVLPRI2		(0x0400)#define INTC_ICONFIG_ELVLPRI3		(0x0800)#define INTC_ICONFIG_ELVLPRI4		(0x1000)#define INTC_ICONFIG_ELVLPRI5		(0x2000)#define INTC_ICONFIG_ELVLPRI6		(0x4000)#define INTC_ICONFIG_ELVLPRI7		(0x8000)/* Bit definitions and macros for SIMR */#define INTC_SIMR_SIMR(x)		(((x)&0x7F))/* Bit definitions and macros for CIMR */#define INTC_CIMR_CIMR(x)		(((x)&0x7F))/* Bit definitions and macros for CLMASK */#define INTC_CLMASK_CLMASK(x)		(((x)&0x0F))/* Bit definitions and macros for SLMASK */#define INTC_SLMASK_SLMASK(x)		(((x)&0x0F))/* Bit definitions and macros for ICR group */#define INTC_ICR_IL(x)			(((x)&0x07))/********************************************************************** Edge Port Module (EPORT)*********************************************************************//* Bit definitions and macros for EPPAR */#define EPORT_EPPAR_EPPA1(x)		(((x)&0x0003)<<2)#define EPORT_EPPAR_EPPA2(x)		(((x)&0x0003)<<4)#define EPORT_EPPAR_EPPA3(x)		(((x)&0x0003)<<6)#define EPORT_EPPAR_EPPA4(x)		(((x)&0x0003)<<8)#define EPORT_EPPAR_EPPA5(x)		(((x)&0x0003)<<10)#define EPORT_EPPAR_EPPA6(x)		(((x)&0x0003)<<12)#define EPORT_EPPAR_EPPA7(x)		(((x)&0x0003)<<14)#define EPORT_EPPAR_LEVEL		(0)#define EPORT_EPPAR_RISING		(1)#define EPORT_EPPAR_FALLING		(2)#define EPORT_EPPAR_BOTH		(3)#define EPORT_EPPAR_EPPA7_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA7_RISING	(0x4000)#define EPORT_EPPAR_EPPA7_FALLING	(0x8000)#define EPORT_EPPAR_EPPA7_BOTH		(0xC000)#define EPORT_EPPAR_EPPA6_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA6_RISING	(0x1000)#define EPORT_EPPAR_EPPA6_FALLING	(0x2000)#define EPORT_EPPAR_EPPA6_BOTH		(0x3000)#define EPORT_EPPAR_EPPA5_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA5_RISING	(0x0400)#define EPORT_EPPAR_EPPA5_FALLING	(0x0800)#define EPORT_EPPAR_EPPA5_BOTH		(0x0C00)#define EPORT_EPPAR_EPPA4_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA4_RISING	(0x0100)#define EPORT_EPPAR_EPPA4_FALLING	(0x0200)#define EPORT_EPPAR_EPPA4_BOTH		(0x0300)#define EPORT_EPPAR_EPPA3_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA3_RISING	(0x0040)#define EPORT_EPPAR_EPPA3_FALLING	(0x0080)#define EPORT_EPPAR_EPPA3_BOTH		(0x00C0)#define EPORT_EPPAR_EPPA2_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA2_RISING	(0x0010)#define EPORT_EPPAR_EPPA2_FALLING	(0x0020)#define EPORT_EPPAR_EPPA2_BOTH		(0x0030)#define EPORT_EPPAR_EPPA1_LEVEL		(0x0000)#define EPORT_EPPAR_EPPA1_RISING	(0x0004)#define EPORT_EPPAR_EPPA1_FALLING	(0x0008)#define EPORT_EPPAR_EPPA1_BOTH		(0x000C)/* Bit definitions and macros for EPDDR */#define EPORT_EPDDR_EPDD1		(0x02)#define EPORT_EPDDR_EPDD2		(0x04)#define EPORT_EPDDR_EPDD3		(0x08)#define EPORT_EPDDR_EPDD4		(0x10)#define EPORT_EPDDR_EPDD5		(0x20)#define EPORT_EPDDR_EPDD6		(0x40)#define EPORT_EPDDR_EPDD7		(0x80)/* Bit definitions and macros for EPIER */#define EPORT_EPIER_EPIE1		(0x02)#define EPORT_EPIER_EPIE2		(0x04)#define EPORT_EPIER_EPIE3		(0x08)#define EPORT_EPIER_EPIE4		(0x10)#define EPORT_EPIER_EPIE5		(0x20)#define EPORT_EPIER_EPIE6		(0x40)#define EPORT_EPIER_EPIE7		(0x80)/* Bit definitions and macros for EPDR */#define EPORT_EPDR_EPD1			(0x02)#define EPORT_EPDR_EPD2			(0x04)#define EPORT_EPDR_EPD3			(0x08)#define EPORT_EPDR_EPD4			(0x10)#define EPORT_EPDR_EPD5			(0x20)#define EPORT_EPDR_EPD6			(0x40)#define EPORT_EPDR_EPD7			(0x80)/* Bit definitions and macros for EPPDR */#define EPORT_EPPDR_EPPD1		(0x02)#define EPORT_EPPDR_EPPD2		(0x04)#define EPORT_EPPDR_EPPD3		(0x08)#define EPORT_EPPDR_EPPD4		(0x10)#define EPORT_EPPDR_EPPD5		(0x20)#define EPORT_EPPDR_EPPD6		(0x40)#define EPORT_EPPDR_EPPD7		(0x80)/* Bit definitions and macros for EPFR */#define EPORT_EPFR_EPF1			(0x02)#define EPORT_EPFR_EPF2			(0x04)#define EPORT_EPFR_EPF3			(0x08)#define EPORT_EPFR_EPF4			(0x10)#define EPORT_EPFR_EPF5			(0x20)#define EPORT_EPFR_EPF6			(0x40)#define EPORT_EPFR_EPF7			(0x80)/********************************************************************** Watchdog Timer Modules (WTM)*********************************************************************//* Bit definitions and macros for WCR */#define WTM_WCR_EN			(0x0001)#define WTM_WCR_HALTED			(0x0002)#define WTM_WCR_DOZE			(0x0004)#define WTM_WCR_WAIT			(0x0008)/********************************************************************** Serial Boot Facility (SBF)*********************************************************************//* Bit definitions and macros for SBFCR */#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))	/* Boot loader clock divider */#define SBF_SBFCR_FR			(0x0010)	/* Fast read *//********************************************************************** Reset Controller Module (RCM)*********************************************************************//* Bit definitions and macros for RCR */#define RCM_RCR_FRCRSTOUT		(0x40)#define RCM_RCR_SOFTRST			(0x80)/* Bit definitions and macros for RSR */#define RCM_RSR_LOL			(0x01)#define RCM_RSR_WDR_CORE		(0x02)#define RCM_RSR_EXT			(0x04)#define RCM_RSR_POR			(0x08)#define RCM_RSR_SOFT			(0x20)/********************************************************************** Chip Configuration Module (CCM)*********************************************************************//* Bit definitions and macros for CCR_360 */#define CCM_CCR_360_PLLMULT2(x)		(((x)&0x0003))	/* 2-Bit PLL clock mode */#define CCM_CCR_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */#define CCM_CCR_360_PCIMODE		(0x0008)	/* PCI host/agent mode */#define CCM_CCR_360_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_CCR_360_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */#define CCM_CCR_360_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL Clock Mode */#define CCM_CCR_360_OSCMODE		(0x0008)	/* Oscillator Clock Mode */#define CCM_CCR_360_FBCONFIG_MASK	(0x00E0)#define CCM_CCR_360_PLLMULT2_MASK	(0x0003)#define CCM_CCR_360_PLLMULT3_MASK	(0x0007)#define CCM_CCR_360_FBCONFIG_NM_NP_32	(0x0000)#define CCM_CCR_360_FBCONFIG_NM_NP_8	(0x0020)#define CCM_CCR_360_FBCONFIG_NM_NP_16	(0x0040)#define CCM_CCR_360_FBCONFIG_M_P_16	(0x0060)#define CCM_CCR_360_FBCONFIG_M_NP_32	(0x0080)#define CCM_CCR_360_FBCONFIG_M_NP_8	(0x00A0)#define CCM_CCR_360_FBCONFIG_M_NP_16	(0x00C0)#define CCM_CCR_360_FBCONFIG_M_P_8	(0x00E0)#define CCM_CCR_360_PLLMULT2_12X	(0x0000)#define CCM_CCR_360_PLLMULT2_6X		(0x0001)#define CCM_CCR_360_PLLMULT2_16X	(0x0002)#define CCM_CCR_360_PLLMULT2_8X		(0x0003)#define CCM_CCR_360_PLLMULT3_20X	(0x0000)#define CCM_CCR_360_PLLMULT3_10X	(0x0001)#define CCM_CCR_360_PLLMULT3_24X	(0x0002)#define CCM_CCR_360_PLLMULT3_18X	(0x0003)#define CCM_CCR_360_PLLMULT3_12X	(0x0004)#define CCM_CCR_360_PLLMULT3_6X		(0x0005)#define CCM_CCR_360_PLLMULT3_16X	(0x0006)#define CCM_CCR_360_PLLMULT3_8X		(0x0007)/* Bit definitions and macros for CCR_256 */#define CCM_CCR_256_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL clock mode */#define CCM_CCR_256_OSCMODE		(0x0008)	/* Oscillator clock mode */#define CCM_CCR_256_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_CCR_256_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */#define CCM_CCR_256_FBCONFIG_MASK	(0x00E0)#define CCM_CCR_256_FBCONFIG_NM_32	(0x0000)#define CCM_CCR_256_FBCONFIG_NM_8	(0x0020)#define CCM_CCR_256_FBCONFIG_NM_16	(0x0040)#define CCM_CCR_256_FBCONFIG_M_32	(0x0080)#define CCM_CCR_256_FBCONFIG_M_8	(0x00A0)#define CCM_CCR_256_FBCONFIG_M_16	(0x00C0)#define CCM_CCR_256_PLLMULT3_MASK	(0x0007)#define CCM_CCR_256_PLLMULT3_20X	(0x0000)#define CCM_CCR_256_PLLMULT3_10X	(0x0001)#define CCM_CCR_256_PLLMULT3_24X	(0x0002)#define CCM_CCR_256_PLLMULT3_18X	(0x0003)#define CCM_CCR_256_PLLMULT3_12X	(0x0004)#define CCM_CCR_256_PLLMULT3_6X		(0x0005)#define CCM_CCR_256_PLLMULT3_16X	(0x0006)#define CCM_CCR_256_PLLMULT3_8X		(0x0007)/* Bit definitions and macros for RCON_360 */#define CCM_RCON_360_PLLMULT(x)		(((x)&0x0003))	/* PLL clock mode */#define CCM_RCON_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */#define CCM_RCON_360_PCIMODE		(0x0008)	/* PCI host/agent mode */#define CCM_RCON_360_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_RCON_360_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration *//* Bit definitions and macros for RCON_256 */#define CCM_RCON_256_PLLMULT(x)		(((x)&0x0007))	/* PLL clock mode */#define CCM_RCON_256_OSCMODE		(0x0008)	/* Oscillator clock mode */#define CCM_RCON_256_PLLMODE		(0x0010)	/* PLL Mode */#define CCM_RCON_256_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration *//* Bit definitions and macros for CIR */#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */#define CCM_CIR_PIN_MASK		(0xFFC0)#define CCM_CIR_PRN_MASK		(0x003F)#define CCM_CIR_PIN_MCF54450		(0x4F<<6)#define CCM_CIR_PIN_MCF54451		(0x4D<<6)#define CCM_CIR_PIN_MCF54452		(0x4B<<6)#define CCM_CIR_PIN_MCF54453		(0x49<<6)#define CCM_CIR_PIN_MCF54454		(0x4A<<6)#define CCM_CIR_PIN_MCF54455		(0x48<<6)/* Bit definitions and macros for MISCCR */#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense polarity */#define CCM_MISCCR_USBPUE		(0x0004)	/* USB transceiver pull-up enable */#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)	/* Bus monitor timing field */#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor external enable bit */#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */#define CCM_MISCCR_BMT_65536		(0)#define CCM_MISCCR_BMT_32768		(1)#define CCM_MISCCR_BMT_16384		(2)#define CCM_MISCCR_BMT_8192		(3)#define CCM_MISCCR_BMT_4096		(4)#define CCM_MISCCR_BMT_2048		(5)#define CCM_MISCCR_BMT_1024		(6)#define CCM_MISCCR_BMT_512		(7)#define CCM_MISCCR_SSIPUS_UP		(1)#define CCM_MISCCR_SSIPUS_DOWN		(0)#define CCM_MISCCR_TIMDMA_TIM		(1)#define CCM_MISCCR_TIMDMA_SSI		(0)#define CCM_MISCCR_SSISRC_CLKIN		(0)#define CCM_MISCCR_SSISRC_PLL		(1)#define CCM_MISCCR_USBOC_ACTHI		(0)#define CCM_MISCCR_USBOV_ACTLO		(1)#define CCM_MISCCR_USBSRC_CLKIN		(0)#define CCM_MISCCR_USBSRC_PLL		(1)/* Bit definitions and macros for CDR */#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clock divider */#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clock divider *//* Bit definitions and macros for UOCSR */#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down enable */#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt enable */#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */#define CCM_UOCSR_PWRFLT		(0x0008)	/* VBUS power fault */#define CCM_UOCSR_SEND			(0x0010)	/* Session end */#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (read-only) */#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor enabled (read-only) */#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (read-only) */#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (read-only) */#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (read-only) *//********************************************************************** General Purpose I/O Module (GPIO)*********************************************************************//* Bit definitions and macros for PAR_FEC */#define GPIO_PAR_FEC_FEC0(x)		(((x)&0x07))#define GPIO_PAR_FEC_FEC1(x)		(((x)&0x07)<<4)#define GPIO_PAR_FEC_FEC1_MASK		(0x8F)#define GPIO_PAR_FEC_FEC1_MII		(0x70)#define GPIO_PAR_FEC_FEC1_RMII_GPIO	(0x30)#define GPIO_PAR_FEC_FEC1_RMII_ATA	(0x20)#define GPIO_PAR_FEC_FEC1_ATA		(0x10)#define GPIO_PAR_FEC_FEC1_GPIO		(0x00)#define GPIO_PAR_FEC_FEC0_MASK		(0xF8)#define GPIO_PAR_FEC_FEC0_MII		(0x07)#define GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)#define GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)#define GPIO_PAR_FEC_FEC0_ULPI		(0x01)#define GPIO_PAR_FEC_FEC0_GPIO		(0x00)/* Bit definitions and macros for PAR_DMA */#define GPIO_PAR_DMA_DREQ0		(0x01)
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