📄 m547x_8x.h
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/* * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef mcf547x_8x_h#define mcf547x_8x_h/********************************************************************** XLB Arbiter (XLB)*********************************************************************//* Bit definitions and macros for XARB_CFG */#define XARB_CFG_AT (0x00000002)#define XARB_CFG_DT (0x00000004)#define XARB_CFG_BA (0x00000008)#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)#define XARB_CFG_PLDIS (0x80000000)/* Bit definitions and macros for XARB_SR */#define XARB_SR_AT (0x00000001)#define XARB_SR_DT (0x00000002)#define XARB_SR_BA (0x00000004)#define XARB_SR_TTM (0x00000008)#define XARB_SR_ECW (0x00000010)#define XARB_SR_TTR (0x00000020)#define XARB_SR_TTA (0x00000040)#define XARB_SR_MM (0x00000080)#define XARB_SR_SEA (0x00000100)/* Bit definitions and macros for XARB_IMR */#define XARB_IMR_ATE (0x00000001)#define XARB_IMR_DTE (0x00000002)#define XARB_IMR_BAE (0x00000004)#define XARB_IMR_TTME (0x00000008)#define XARB_IMR_ECWE (0x00000010)#define XARB_IMR_TTRE (0x00000020)#define XARB_IMR_TTAE (0x00000040)#define XARB_IMR_MME (0x00000080)#define XARB_IMR_SEAE (0x00000100)/* Bit definitions and macros for XARB_SIGCAP */#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)#define XARB_SIGCAP_TBST (0x00000020)#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)/* Bit definitions and macros for XARB_PRIEN */#define XARB_PRIEN_M0 (0x00000001)#define XARB_PRIEN_M2 (0x00000004)#define XARB_PRIEN_M3 (0x00000008)/* Bit definitions and macros for XARB_PRI */#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)/********************************************************************** General Purpose I/O (GPIO)*********************************************************************//* Bit definitions and macros for GPIO_PAR_FBCTL */#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)#define GPIO_PAR_FBCTL_TA (0x0004)#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)#define GPIO_PAR_FBCTL_OE (0x0040)#define GPIO_PAR_FBCTL_BWE0 (0x0100)#define GPIO_PAR_FBCTL_BWE1 (0x0400)#define GPIO_PAR_FBCTL_BWE2 (0x1000)#define GPIO_PAR_FBCTL_BWE3 (0x4000)#define GPIO_PAR_FBCTL_TS_GPIO (0)#define GPIO_PAR_FBCTL_TS_TBST (2)#define GPIO_PAR_FBCTL_TS_TS (3)#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)/* Bit definitions and macros for GPIO_PAR_FBCS */#define GPIO_PAR_FBCS_CS1 (0x02)#define GPIO_PAR_FBCS_CS2 (0x04)#define GPIO_PAR_FBCS_CS3 (0x08)#define GPIO_PAR_FBCS_CS4 (0x10)#define GPIO_PAR_FBCS_CS5 (0x20)/* Bit definitions and macros for GPIO_PAR_DMA */#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)#define GPIO_PAR_DMA_DACKx_GPIO (0)#define GPIO_PAR_DMA_DACKx_TOUT (2)#define GPIO_PAR_DMA_DACKx_DACK (3)#define GPIO_PAR_DMA_DREQx_GPIO (0)#define GPIO_PAR_DMA_DREQx_TIN (2)#define GPIO_PAR_DMA_DREQx_DREQ (3)/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)/* Bit definitions and macros for GPIO_PAR_PCIBG */#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)/* Bit definitions and macros for GPIO_PAR_PCIBR */#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)/* Bit definitions and macros for GPIO_PAR_PSC3 */#define GPIO_PAR_PSC3_TXD3 (0x04)#define GPIO_PAR_PSC3_RXD3 (0x08)#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)#define GPIO_PAR_PSC3_RTS3_RTS (0x30)#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)/* Bit definitions and macros for GPIO_PAR_PSC2 */#define GPIO_PAR_PSC2_TXD2 (0x04)#define GPIO_PAR_PSC2_RXD2 (0x08)#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)#define GPIO_PAR_PSC2_RTS2_RTS (0x30)/* Bit definitions and macros for GPIO_PAR_PSC1 */#define GPIO_PAR_PSC1_TXD1 (0x04)#define GPIO_PAR_PSC1_RXD1 (0x08)#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)#define GPIO_PAR_PSC1_RTS1_RTS (0x30)/* Bit definitions and macros for GPIO_PAR_PSC0 */#define GPIO_PAR_PSC0_TXD0 (0x04)#define GPIO_PAR_PSC0_RXD0 (0x08)#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)#define GPIO_PAR_PSC0_RTS0_RTS (0x30)/* Bit definitions and macros for GPIO_PAR_DSPI */#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)#define GPIO_PAR_DSPI_CS5 (0x1000)#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)#define GPIO_PAR_DSPI_CS0_RTS (0x0080)#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)#define GPIO_PAR_DSPI_SCK_CTS (0x0020)#define GPIO_PAR_DSPI_SCK_SCK (0x0030)#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)#define GPIO_PAR_DSPI_SIN_RXD (0x0008)#define GPIO_PAR_DSPI_SIN_SIN (0x000C)#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)/* Bit definitions and macros for GPIO_PAR_TIMER */#define GPIO_PAR_TIMER_TOUT2 (0x01)#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)#define GPIO_PAR_TIMER_TOUT3 (0x08)#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)#define GPIO_PAR_TIMER_TIN3_TIN (0x30)#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)#define GPIO_PAR_TIMER_TIN2_TIN (0x06)/********************************************************************** Slice Timer (SLT)*********************************************************************/#define SLT_CR_RUN (0x04000000)#define SLT_CR_IEN (0x02000000)#define SLT_CR_TEN (0x01000000)#define SLT_SR_BE (0x02000000)#define SLT_SR_ST (0x01000000)/*********************************************************************⌨️ 快捷键说明
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