📄 m5329.h
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#define GPIO_PCLRR_PWM_5 (0x20)/* Bit definitions and macros for GPIO_PCLRR_FECI2C */#define GPIO_PCLRR_FECI2C_0 (0x01)#define GPIO_PCLRR_FECI2C_1 (0x02)#define GPIO_PCLRR_FECI2C_2 (0x04)#define GPIO_PCLRR_FECI2C_3 (0x08)/* Bit definitions and macros for GPIO_PCLRR_UART */#define GPIO_PCLRR_UART0 (0x01)#define GPIO_PCLRR_UART1 (0x02)#define GPIO_PCLRR_UART2 (0x04)#define GPIO_PCLRR_UART3 (0x08)#define GPIO_PCLRR_UART4 (0x10)#define GPIO_PCLRR_UART5 (0x20)#define GPIO_PCLRR_UART6 (0x40)#define GPIO_PCLRR_UART7 (0x80)/* Bit definitions and macros for GPIO_PCLRR_QSPI */#define GPIO_PCLRR_QSPI0 (0x01)#define GPIO_PCLRR_QSPI1 (0x02)#define GPIO_PCLRR_QSPI2 (0x04)#define GPIO_PCLRR_QSPI3 (0x08)#define GPIO_PCLRR_QSPI4 (0x10)#define GPIO_PCLRR_QSPI5 (0x20)/* Bit definitions and macros for GPIO_PCLRR_TIMER */#define GPIO_PCLRR_TIMER0 (0x01)#define GPIO_PCLRR_TIMER1 (0x02)#define GPIO_PCLRR_TIMER2 (0x04)#define GPIO_PCLRR_TIMER3 (0x08)/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */#define GPIO_PCLRR_LCDDATAH0 (0x01)#define GPIO_PCLRR_LCDDATAH1 (0x02)/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */#define GPIO_PCLRR_LCDDATAM0 (0x01)#define GPIO_PCLRR_LCDDATAM1 (0x02)#define GPIO_PCLRR_LCDDATAM2 (0x04)#define GPIO_PCLRR_LCDDATAM3 (0x08)#define GPIO_PCLRR_LCDDATAM4 (0x10)#define GPIO_PCLRR_LCDDATAM5 (0x20)#define GPIO_PCLRR_LCDDATAM6 (0x40)#define GPIO_PCLRR_LCDDATAM7 (0x80)/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */#define GPIO_PCLRR_LCDDATAL0 (0x01)#define GPIO_PCLRR_LCDDATAL1 (0x02)#define GPIO_PCLRR_LCDDATAL2 (0x04)#define GPIO_PCLRR_LCDDATAL3 (0x08)#define GPIO_PCLRR_LCDDATAL4 (0x10)#define GPIO_PCLRR_LCDDATAL5 (0x20)#define GPIO_PCLRR_LCDDATAL6 (0x40)#define GPIO_PCLRR_LCDDATAL7 (0x80)/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */#define GPIO_PCLRR_LCDCTLL0 (0x01)#define GPIO_PCLRR_LCDCTLL1 (0x02)#define GPIO_PCLRR_LCDCTLL2 (0x04)#define GPIO_PCLRR_LCDCTLL3 (0x08)#define GPIO_PCLRR_LCDCTLL4 (0x10)#define GPIO_PCLRR_LCDCTLL5 (0x20)#define GPIO_PCLRR_LCDCTLL6 (0x40)#define GPIO_PCLRR_LCDCTLL7 (0x80)/* Bit definitions and macros for GPIO_PAR_FEC */#ifdef CONFIG_M5329#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)#define GPIO_PAR_FEC_7W_GPIO (0x00)#define GPIO_PAR_FEC_7W_URTS1 (0x04)#define GPIO_PAR_FEC_7W_FEC (0x0C)#define GPIO_PAR_FEC_MII_GPIO (0x00)#define GPIO_PAR_FEC_MII_UART (0x01)#define GPIO_PAR_FEC_MII_FEC (0x03)#else#define GPIO_PAR_FEC_7W_FEC (0x08)#define GPIO_PAR_FEC_MII_FEC (0x02)#endif/* Bit definitions and macros for GPIO_PAR_PWM */#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2)#define GPIO_PAR_PWM5 (0x10)#define GPIO_PAR_PWM7 (0x20)/* Bit definitions and macros for GPIO_PAR_BUSCTL */#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3)#define GPIO_PAR_BUSCTL_RWB (0x20)#define GPIO_PAR_BUSCTL_TA (0x40)#define GPIO_PAR_BUSCTL_OE (0x80)#define GPIO_PAR_BUSCTL_OE_GPIO (0x00)#define GPIO_PAR_BUSCTL_OE_OE (0x80)#define GPIO_PAR_BUSCTL_TA_GPIO (0x00)#define GPIO_PAR_BUSCTL_TA_TA (0x40)#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00)#define GPIO_PAR_BUSCTL_RWB_RWB (0x20)#define GPIO_PAR_BUSCTL_TS_GPIO (0x00)#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10)#define GPIO_PAR_BUSCTL_TS_TS (0x18)/* Bit definitions and macros for GPIO_PAR_FECI2C */#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0)#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4)#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6)#define GPIO_PAR_FECI2C_MDC_GPIO (0x00)#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40)#define GPIO_PAR_FECI2C_MDC_SCL (0x80)#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0)#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00)#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10)#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30)#define GPIO_PAR_FECI2C_SCL_GPIO (0x00)#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04)#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)#define GPIO_PAR_FECI2C_SDA_GPIO (0x00)#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02)#define GPIO_PAR_FECI2C_SDA_SDA (0x03)/* Bit definitions and macros for GPIO_PAR_BE */#define GPIO_PAR_BE0 (0x01)#define GPIO_PAR_BE1 (0x02)#define GPIO_PAR_BE2 (0x04)#define GPIO_PAR_BE3 (0x08)/* Bit definitions and macros for GPIO_PAR_CS */#define GPIO_PAR_CS1 (0x02)#define GPIO_PAR_CS2 (0x04)#define GPIO_PAR_CS3 (0x08)#define GPIO_PAR_CS4 (0x10)#define GPIO_PAR_CS5 (0x20)#define GPIO_PAR_CS1_GPIO (0x00)#define GPIO_PAR_CS1_SDCS1 (0x01)#define GPIO_PAR_CS1_CS1 (0x03)/* Bit definitions and macros for GPIO_PAR_SSI */#define GPIO_PAR_SSI_MCLK (0x0080)#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8)#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10)#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12)#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14)/* Bit definitions and macros for GPIO_PAR_UART */#define GPIO_PAR_UART_TXD0 (0x0001)#define GPIO_PAR_UART_RXD0 (0x0002)#define GPIO_PAR_UART_RTS0 (0x0004)#define GPIO_PAR_UART_CTS0 (0x0008)#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4)#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6)#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8)#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10)#define GPIO_PAR_UART_CTS1_GPIO (0x0000)#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800)#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400)#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00)#define GPIO_PAR_UART_RTS1_GPIO (0x0000)#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200)#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100)#define GPIO_PAR_UART_RTS1_URTS1 (0x0300)#define GPIO_PAR_UART_RXD1_GPIO (0x0000)#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080)#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040)#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0)#define GPIO_PAR_UART_TXD1_GPIO (0x0000)#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020)#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010)#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030)/* Bit definitions and macros for GPIO_PAR_QSPI */#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4)#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6)#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8)#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10)#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12)#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14)/* Bit definitions and macros for GPIO_PAR_TIMER */#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0)#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2)#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4)#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6)#define GPIO_PAR_TIN3_GPIO (0x00)#define GPIO_PAR_TIN3_TOUT3 (0x80)#define GPIO_PAR_TIN3_URXD2 (0x40)#define GPIO_PAR_TIN3_TIN3 (0xC0)#define GPIO_PAR_TIN2_GPIO (0x00)#define GPIO_PAR_TIN2_TOUT2 (0x20)#define GPIO_PAR_TIN2_UTXD2 (0x10)#define GPIO_PAR_TIN2_TIN2 (0x30)#define GPIO_PAR_TIN1_GPIO (0x00)#define GPIO_PAR_TIN1_TOUT1 (0x08)#define GPIO_PAR_TIN1_DACK1 (0x04)#define GPIO_PAR_TIN1_TIN1 (0x0C)#define GPIO_PAR_TIN0_GPIO (0x00)#define GPIO_PAR_TIN0_TOUT0 (0x02)#define GPIO_PAR_TIN0_DREQ0 (0x01)#define GPIO_PAR_TIN0_TIN0 (0x03)/* Bit definitions and macros for GPIO_PAR_LCDDATA */#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03)#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2)#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4)#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6)/* Bit definitions and macros for GPIO_PAR_LCDCTL */#define GPIO_PAR_LCDCTL_CLS (0x0001)#define GPIO_PAR_LCDCTL_PS (0x0002)#define GPIO_PAR_LCDCTL_REV (0x0004)#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008)#define GPIO_PAR_LCDCTL_CONTRAST (0x0010)#define GPIO_PAR_LCDCTL_LSCLK (0x0020)#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040)#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080)#define GPIO_PAR_LCDCTL_ACD_OE (0x0100)/* Bit definitions and macros for GPIO_PAR_IRQ */#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4)#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6)#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8)#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10)#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12)/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03)#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2)#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4)/* Bit definitions and macros for GPIO_MSCR_SDRAM */#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03)#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4)/* Bit definitions and macros for GPIO_DSCR_I2C */#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_PWM */#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_FEC */#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_UART */#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03)#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2)/* Bit definitions and macros for GPIO_DSCR_QSPI */#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_TIMER */#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_SSI */#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_LCD */#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_DEBUG */#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_CLKRST */#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03)/* Bit definitions and macros for GPIO_DSCR_IRQ */#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)/********************************************************************** SDRAM Controller (SDRAMC)*********************************************************************//* Bit definitions and macros for SDRAMC_SDMR */#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000)#define SDRAMC_SDMR_BNKAD_LMR (0x00000000)#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)#define SDRAMC_SDMR_CMD (0x00010000)/* Bit definitions and macros for SDRAMC_SDCR */#define SDRAMC_SDCR_MODE_EN (0x80000000)#define SDRAMC_SDCR_CKE (0x40000000)#define SDRAMC_SDCR_DDR (0x20000000)#define SDRAMC_SDCR_REF (0x10000000)#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)#define SDRAMC_SDCR_OE_RULE (0x00400000)#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)#define SDRAMC_SDCR_PS_32 (0x00000000)#define SDRAMC_SDCR_PS_16 (0x00002000)#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)#define SDRAMC_SDCR_IREF (0x00000004)#define SDRAMC_SDCR_IPALL (0x00000002)/* Bit definitions and macros for SDRAMC_SDCFG1 */#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)/* Bit definitions and macros for SDRAMC_SDCFG2 */#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)/* Bit definitions and macros for SDRAMC_SDDS */#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003)/* Bit definitions and macros for SDRAMC_SDCS */#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F)#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)/********************************************************************** Phase Locked Loop (PLL)*********************************************************************//* Bit definitions and macros for PLL_PODR */#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)#define PLL_PODR_BUSDIV(x) ((x)&0x0F)/* Bit definitions and macros for PLL_PLLCR */#define PLL_PLLCR_DITHEN (0x80)#define PLL_PLLCR_DITHDEV(x) ((x)&0x07)#endif /* mcf5329_h */⌨️ 快捷键说明
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