tables.h

uboot详细解读可用启动引导LINUX2.6内核

    0,		     "mftb",	     0 },
  { X_OPCODE(31,375,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
    0,		     "lhaux",	     0 },
  { X_OPCODE(31,407,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
    0,		     "sthx",	     H_RA0_IS_0 },
  { X_OPCODE(31,412,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "orc",	     0 },
  { X_OPCODE(31,412,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "orc.",	     0 },
  { X_OPCODE(31,438,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
    0,		     "ecowx",	     H_RA0_IS_0 },
  { X_OPCODE(31,439,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
    0,		     "sthux",	     0 },
  { X_OPCODE(31,444,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "or",	     0 },
  { X_OPCODE(31,444,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "or.",	     0 },
  { XO_OPCODE(31,459,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divwu",	     0 },
  { XO_OPCODE(31,459,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divwu.",	     0 },
  { XFX_OPCODE(31,467,0),  XFX_MASK, {O_spr, O_rS, 0},
    0,		     "mtspr",	     0 },
  { X_OPCODE(31,470,0),    X_MASK,   {O_rA, O_rB, 0},
    0,		     "dcbi",	     H_RA0_IS_0 },
  { X_OPCODE(31,476,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "nand",	     0 },
  { X_OPCODE(31,476,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc,0},
    0,		     "nand.",	     0 },
  { XO_OPCODE(31,491,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divw",	     0 },
  { XO_OPCODE(31,491,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divw.",	     0 },
  { X_OPCODE(31,512,0),    X_MASK,   {O_crfD, 0},
    0,		     "mcrxr",	     0 },
  { XO_OPCODE(31,8,1,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "subfco",	     0 },
  { XO_OPCODE(31,8,1,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "subfco.",      0 },
  { XO_OPCODE(31,10,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "addco",	     0 },
  { XO_OPCODE(31,10,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "addco.",	     0 },
  { X_OPCODE(31,533,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
    0,		     "lswx",	     H_RA0_IS_0 },
  { X_OPCODE(31,534,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
    0,		     "lwbrx",	     H_RA0_IS_0 },
  { X_OPCODE(31,536,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "srw",	     0 },
  { X_OPCODE(31,536,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "srw.",	     0 },
  { XO_OPCODE(31,40,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "subfo",	     0 },
  { XO_OPCODE(31,40,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "subfo.",	     0 },
  { X_OPCODE(31,566,0),    X_MASK,   {0},
    0,		     "tlbsync",      0 },
  { X_OPCODE(31,595,0),    X_MASK,   {O_rD, O_SR, 0},
    0,		     "mfsr",	     0 },
  { X_OPCODE(31,597,0),    X_MASK,   {O_rD, O_rA, O_NB, 0},
    0,		     "lswi",	     H_RA0_IS_0 },
  { X_OPCODE(31,598,0),    X_MASK,   {0},
    0,		     "sync",	     0 },
  { XO_OPCODE(31,104,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "nego",	     0 },
  { XO_OPCODE(31,104,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "nego.",	     0 },
  { XO_OPCODE(31,136,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "subfeo",	     0 },
  { XO_OPCODE(31,136,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "subfeo.",      0 },
  { XO_OPCODE(31,138,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "addeo",	     0 },
  { XO_OPCODE(31,138,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "addeo.",	     0 },
  { X_OPCODE(31,659,0),    X_MASK,   {O_rD, O_rB, 0},
    0,		     "mfsrin",	     0 },
  { X_OPCODE(31,661,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
    0,		     "stswx",	     H_RA0_IS_0 },
  { X_OPCODE(31,662,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
    0,		     "stwbrx",	     H_RA0_IS_0 },
  { XO_OPCODE(31,200,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "subfzeo",      0 },
  { XO_OPCODE(31,200,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "subfzeo.",     0 },
  { XO_OPCODE(31,202,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "addzeo",	     0 },
  { XO_OPCODE(31,202,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "addzeo.",      0 },
  { X_OPCODE(31,725,0),    X_MASK,   {O_rS, O_rA, O_NB, 0},
    0,		     "stswi",	     H_RA0_IS_0 },
  { XO_OPCODE(31,232,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "subfmeo",      0 },
  { XO_OPCODE(31,232,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "subfmeo.",     0 },
  { XO_OPCODE(31,234,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "addmeo",	     0 },
  { XO_OPCODE(31,234,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
    0,		     "addmeo.",      0 },
  { XO_OPCODE(31,235,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "mullwo",	     0 },
  { XO_OPCODE(31,235,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "mullwo.",      0 },
  { XO_OPCODE(31,266,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "addo",	     0 },
  { XO_OPCODE(31,266,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "addo.",	     0 },
  { X_OPCODE(31,790,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
    0,		     "lhbrx",	     H_RA0_IS_0 },
  { X_OPCODE(31,792,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "sraw",	     0 },
  { X_OPCODE(31,792,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
    0,		     "sraw.",	     0 },
  { X_OPCODE(31,824,0),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
    0,		     "srawi",	     0 },
  { X_OPCODE(31,824,1),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
    0,		     "srawi.",	     0 },
  { X_OPCODE(31,854,0),    X_MASK,   {0},
    0,		     "eieio",	     0 },
  { X_OPCODE(31,918,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
    0,		     "sthbrx",	     H_RA0_IS_0 },
  { X_OPCODE(31,922,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
    0,		     "extsh",	     0 },
  { X_OPCODE(31,922,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
    0,		     "extsh.",	     0 },
  { X_OPCODE(31,954,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
    0,		     "extsb",	     0 },
  { X_OPCODE(31,954,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
    0,		     "extsb.",	     0 },
  { XO_OPCODE(31,459,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divwuo",	     0 },
  { XO_OPCODE(31,459,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divwuo.",      0 },
  { X_OPCODE(31,978,0),    X_MASK,   {O_rB, 0},
    0,		     "tlbld",	     0 },
  { X_OPCODE(31,982,0),    X_MASK,   {O_rA, O_rB, 0},
    0,		     "icbi",	     H_RA0_IS_0 },
  { XO_OPCODE(31,491,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divwo",	     0 },
  { XO_OPCODE(31,491,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
    0,		     "divwo.",	     0 },
  { X_OPCODE(31,1010,0),   X_MASK,   {O_rB, 0},
    0,		     "tlbli",	     0 },
  { X_OPCODE(31,1014,0),   X_MASK,   {O_rA, O_rB, 0},
    0,		     "dcbz",	     H_RA0_IS_0 },
  { D_OPCODE(32),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lwz",	     H_RA0_IS_0 },
  { D_OPCODE(33),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lwzu",	     0 },
  { D_OPCODE(34),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lbz",	     H_RA0_IS_0 },
  { D_OPCODE(35),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lbzu",	     0 },
  { D_OPCODE(36),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "stw",	     H_RA0_IS_0 },
  { D_OPCODE(37),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "stwu",	     0 },
  { D_OPCODE(38),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "stb",	     H_RA0_IS_0 },
  { D_OPCODE(39),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "stbu",	     0 },
  { D_OPCODE(40),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lhz",	     H_RA0_IS_0 },
  { D_OPCODE(41),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lhzu",	     0 },
  { D_OPCODE(42),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lha",	     H_RA0_IS_0 },
  { D_OPCODE(43),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lhau",	     0 },
  { D_OPCODE(44),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "sth",	     H_RA0_IS_0 },
  { D_OPCODE(45),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "sthu",	     0 },
  { D_OPCODE(46),	   D_MASK,   {O_rD, O_d, O_rA, 0},
    0,		     "lmw",	     H_RA0_IS_0 },
  { D_OPCODE(47),	   D_MASK,   {O_rS, O_d, O_rA, 0},
    0,		     "stmw",	     H_RA0_IS_0 },
};

const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);

struct spr_info spr_map[] = {
  { SPR_XER,	"XER" },
  { SPR_LR,	"LR" },
  { SPR_CTR,	"CTR" },
  { SPR_DSISR,	"DSISR" },
  { SPR_DAR,	"DAR" },
  { SPR_DEC,	"DEC" },
  { SPR_SRR0,	"SRR0" },
  { SPR_SRR1,	"SRR1" },
  { SPR_EIE,	"EIE" },
  { SPR_EID,	"EID" },
  { SPR_CMPA,	"CMPA" },
  { SPR_CMPB,	"CMPB" },
  { SPR_CMPC,	"CMPC" },
  { SPR_CMPD,	"CMPD" },
  { SPR_ICR,	"ICR" },
  { SPR_DER,	"DER" },
  { SPR_COUNTA,	"COUNTA" },
  { SPR_COUNTB,	"COUNTB" },
  { SPR_CMPE,	"CMPE" },
  { SPR_CMPF,	"CMPF" },
  { SPR_CMPG,	"CMPG" },
  { SPR_CMPH,	"CMPH" },
  { SPR_LCTRL1,	"LCTRL1" },
  { SPR_LCTRL2,	"LCTRL2" },
  { SPR_ICTRL,	"ICTRL" },
  { SPR_BAR,	"BAR" },
  { SPR_USPRG0,	"USPRG0" },
  { SPR_SPRG4_RO,	"SPRG4_RO" },
  { SPR_SPRG5_RO,	"SPRG5_RO" },
  { SPR_SPRG6_RO,	"SPRG6_RO" },
  { SPR_SPRG7_RO,	"SPRG7_RO" },
  { SPR_SPRG0,	"SPRG0" },
  { SPR_SPRG1,	"SPRG1" },
  { SPR_SPRG2,	"SPRG2" },
  { SPR_SPRG3,	"SPRG3" },
  { SPR_SPRG4,	"SPRG4" },
  { SPR_SPRG5,	"SPRG5" },
  { SPR_SPRG6,	"SPRG6" },
  { SPR_SPRG7,	"SPRG7" },
  { SPR_EAR,	"EAR" },
  { SPR_TBL,	"TBL" },
  { SPR_TBU,	"TBU" },
  { SPR_IC_CST,	"IC_CST" },
  { SPR_IC_ADR,	"IC_ADR" },
  { SPR_IC_DAT,	"IC_DAT" },
  { SPR_DC_CST,	"DC_CST" },
  { SPR_DC_ADR,	"DC_ADR" },
  { SPR_DC_DAT,	"DC_DAT" },
  { SPR_DPDR,	"DPDR" },
  { SPR_IMMR,	"IMMR" },
  { SPR_MI_CTR,	"MI_CTR" },
  { SPR_MI_AP,	"MI_AP" },
  { SPR_MI_EPN,	"MI_EPN" },
  { SPR_MI_TWC,	"MI_TWC" },
  { SPR_MI_RPN,	"MI_RPN" },
  { SPR_MD_CTR,	"MD_CTR" },
  { SPR_M_CASID,	"M_CASID" },
  { SPR_MD_AP,	"MD_AP" },
  { SPR_MD_EPN,	"MD_EPN" },
  { SPR_M_TWB,	"M_TWB" },
  { SPR_MD_TWC,	"MD_TWC" },
  { SPR_MD_RPN,	"MD_RPN" },
  { SPR_M_TW,	"M_TW" },
  { SPR_MI_DBCAM,	"MI_DBCAM" },
  { SPR_MI_DBRAM0,	"MI_DBRAM0" },
  { SPR_MI_DBRAM1,	"MI_DBRAM1" },
  { SPR_MD_DBCAM,	"MD_DBCAM" },
  { SPR_MD_DBRAM0,	"MD_DBRAM0" },
  { SPR_MD_DBRAM1,	"MD_DBRAM1" },
  { SPR_ZPR,	"ZPR" },
  { SPR_PID,	"PID" },
  { SPR_CCR0,	"CCR0" },
  { SPR_IAC3,	"IAC3" },
  { SPR_IAC4,	"IAC4" },
  { SPR_DVC1,	"DVC1" },
  { SPR_DVC2,	"DVC2" },
  { SPR_SGR,	"SGR" },
  { SPR_DCWR,	"DCWR" },
  { SPR_SLER,	"SLER" },
  { SPR_SU0R,	"SU0R" },
  { SPR_DBCR1,	"DBCR1" },
  { SPR_ICDBDR,	"ICDBDR" },
  { SPR_ESR,	"ESR" },
  { SPR_DEAR,	"DEAR" },
  { SPR_EVPR,	"EVPR" },
  { SPR_TSR,	"TSR" },
  { SPR_TCR,	"TCR" },
  { SPR_PIT,	"PIT" },
  { SPR_SRR2,	"SRR2" },
  { SPR_SRR3,	"SRR3" },
  { SPR_DBSR,	"DBSR" },
  { SPR_DBCR0,	"DBCR0" },
  { SPR_IAC1,	"IAC1" },
  { SPR_IAC2,	"IAC2" },
  { SPR_DAC1,	"DAC1" },
  { SPR_DAC2,	"DAC2" },
  { SPR_DCCR,	"DCCR" },
  { SPR_ICCR,	"ICCR" },
};

const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);

#endif

/*
 * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms are freely
 * permitted provided that the above copyright notice and this
 * paragraph and the following disclaimer are duplicated in all
 * such forms.
 *
 * This software is provided "AS IS" and without any express or
 * implied warranties, including, without limitation, the implied
 * warranties of merchantability and fitness for a particular
 * purpose.
 */