ppc440.h
来自「uboot详细解读可用启动引导LINUX2.6内核」· C头文件 代码 · 共 1,185 行 · 第 1/5 页
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#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In *//* USB Control Register */#define SDR0_USB0 0x0320#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable *//* Miscealleneaous Function Reg. */#define SDR0_MFR 0x4300#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)#define SDR0_MFR_ERRATA3_EN0 0x00800000#define SDR0_MFR_ERRATA3_EN1 0x00400000#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */#define GPT0_COMP6 0x00000098#define GPT0_COMP5 0x00000094#define GPT0_COMP4 0x00000090#define GPT0_COMP3 0x0000008C#define GPT0_COMP2 0x00000088#define GPT0_COMP1 0x00000084#define GPT0_MASK6 0x000000D8#define GPT0_MASK5 0x000000D4#define GPT0_MASK4 0x000000D0#define GPT0_MASK3 0x000000CC#define GPT0_MASK2 0x000000C8#define GPT0_MASK1 0x000000C4#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)#define SDR0_USB2D0CR 0x0320#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable *//* USB2 Host Control Register */#define SDR0_USB2H0CR 0x0340#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment *//* Pin Function Control Register 1 */#define SDR0_PFC1 0x4101#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In *//* Ethernet PLL Configuration Register */#define SDR0_PFC2 0x4102#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */#define SDR0_PFC4 0x4104/* USB2PHY0 Control Register */#define SDR0_USB2PHY0CR 0x4103#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*//* Miscealleneaous Function Reg. */#define SDR0_MFR 0x4300#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)#define SDR0_MFR_ERRATA3_EN0 0x00800000#define SDR0_MFR_ERRATA3_EN1 0x00400000#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) *//* CUST1 Customer Configuration Register1 */#define SDR0_CUST1 0x4002#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)/* Pin Function Control Register 0 */#define SDR0_PFC0 0x4100#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)⌨️ 快捷键说明
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