ppc440.h
来自「uboot详细解读可用启动引导LINUX2.6内核」· C头文件 代码 · 共 1,185 行 · 第 1/5 页
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#define MMUCR_SWOA 0x01000000#define MMUCR_U1TE 0x00400000#define MMUCR_U2SWOAE 0x00200000#define MMUCR_DULXE 0x00800000#define MMUCR_IULXE 0x00400000#define MMUCR_STS 0x00100000#define MMUCR_STID_MASK 0x000000FF#ifdef CONFIG_440SPE#undef sdr_sdstp2#define sdr_sdstp2 0x0022#undef sdr_sdstp3#define sdr_sdstp3 0x0023#define sdr_ddr0 0x00E1#define sdr_uart2 0x0122#define sdr_xcr0 0x01c0/* #define sdr_xcr1 0x01c3 only one PCIX - SG *//* #define sdr_xcr2 0x01c6 only one PCIX - SG */#define sdr_xpllc0 0x01c1#define sdr_xplld0 0x01c2#define sdr_xpllc1 0x01c4 /*notRCW - SG */#define sdr_xplld1 0x01c5 /*notRCW - SG */#define sdr_xpllc2 0x01c7 /*notRCW - SG */#define sdr_xplld2 0x01c8 /*notRCW - SG */#define sdr_amp0 0x0240#define sdr_amp1 0x0241#define sdr_cust2 0x4004#define sdr_cust3 0x4006#define sdr_sdstp4 0x4001#define sdr_sdstp5 0x4003#define sdr_sdstp6 0x4005#define sdr_sdstp7 0x4007/****************************************************************************** * PCI express defines ******************************************************************************/#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */#endif /* CONFIG_440SPE *//*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*//* values for ebccfga register - indirect addressing of these regs */#define pb0cr 0x00 /* periph bank 0 config reg */#define pb1cr 0x01 /* periph bank 1 config reg */#define pb2cr 0x02 /* periph bank 2 config reg */#define pb3cr 0x03 /* periph bank 3 config reg */#define pb4cr 0x04 /* periph bank 4 config reg */#define pb5cr 0x05 /* periph bank 5 config reg */#define pb6cr 0x06 /* periph bank 6 config reg */#define pb7cr 0x07 /* periph bank 7 config reg */#define pb0ap 0x10 /* periph bank 0 access parameters */#define pb1ap 0x11 /* periph bank 1 access parameters */#define pb2ap 0x12 /* periph bank 2 access parameters */#define pb3ap 0x13 /* periph bank 3 access parameters */#define pb4ap 0x14 /* periph bank 4 access parameters */#define pb5ap 0x15 /* periph bank 5 access parameters */#define pb6ap 0x16 /* periph bank 6 access parameters */#define pb7ap 0x17 /* periph bank 7 access parameters */#define pbear 0x20 /* periph bus error addr reg */#define pbesr 0x21 /* periph bus error status reg */#define xbcfg 0x23 /* external bus configuration reg */#define EBC0_CFG 0x23 /* external bus configuration reg */#define xbcid 0x24 /* external bus core id reg */#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)/* PLB4 to PLB3 Bridge OUT */#define P4P3_DCR_BASE 0x020#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)#define p4p3_eadr (P4P3_DCR_BASE+0x2)#define p4p3_euadr (P4P3_DCR_BASE+0x3)#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)#define p4p3_confg (P4P3_DCR_BASE+0x6)#define p4p3_pic (P4P3_DCR_BASE+0x7)#define p4p3_peir (P4P3_DCR_BASE+0x8)#define p4p3_rev (P4P3_DCR_BASE+0xA)/* PLB3 to PLB4 Bridge IN */#define P3P4_DCR_BASE 0x030#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)#define p3p4_eadr (P3P4_DCR_BASE+0x2)#define p3p4_euadr (P3P4_DCR_BASE+0x3)#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)#define p3p4_confg (P3P4_DCR_BASE+0x6)#define p3p4_pic (P3P4_DCR_BASE+0x7)#define p3p4_peir (P3P4_DCR_BASE+0x8)#define p3p4_rev (P3P4_DCR_BASE+0xA)/* PLB3 Arbiter */#define PLB3_DCR_BASE 0x070#define plb3_revid (PLB3_DCR_BASE+0x2)#define plb3_besr (PLB3_DCR_BASE+0x3)#define plb3_bear (PLB3_DCR_BASE+0x6)#define plb3_acr (PLB3_DCR_BASE+0x7)/* PLB4 Arbiter - PowerPC440EP Pass1 */#define PLB4_DCR_BASE 0x080#define plb4_acr (PLB4_DCR_BASE+0x1)#define plb4_revid (PLB4_DCR_BASE+0x2)#define plb4_besr (PLB4_DCR_BASE+0x4)#define plb4_bearl (PLB4_DCR_BASE+0x6)#define plb4_bearh (PLB4_DCR_BASE+0x7)#define PLB4_ACR_WRP (0x80000000 >> 7)/* Nebula PLB4 Arbiter - PowerPC440EP */#define PLB_ARBITER_BASE 0x80#define plb0_revid (PLB_ARBITER_BASE+ 0x00)#define plb0_acr (PLB_ARBITER_BASE+ 0x01)#define plb0_acr_ppm_mask 0xF0000000#define plb0_acr_ppm_fixed 0x00000000#define plb0_acr_ppm_fair 0xD0000000#define plb0_acr_hbu_mask 0x08000000#define plb0_acr_hbu_disabled 0x00000000#define plb0_acr_hbu_enabled 0x08000000#define plb0_acr_rdp_mask 0x06000000#define plb0_acr_rdp_disabled 0x00000000#define plb0_acr_rdp_2deep 0x02000000#define plb0_acr_rdp_3deep 0x04000000#define plb0_acr_rdp_4deep 0x06000000#define plb0_acr_wrp_mask 0x01000000#define plb0_acr_wrp_disabled 0x00000000#define plb0_acr_wrp_2deep 0x01000000#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)#define plb1_acr (PLB_ARBITER_BASE+ 0x09)#define plb1_acr_ppm_mask 0xF0000000#define plb1_acr_ppm_fixed 0x00000000#define plb1_acr_ppm_fair 0xD0000000#define plb1_acr_hbu_mask 0x08000000#define plb1_acr_hbu_disabled 0x00000000#define plb1_acr_hbu_enabled 0x08000000#define plb1_acr_rdp_mask 0x06000000#define plb1_acr_rdp_disabled 0x00000000#define plb1_acr_rdp_2deep 0x02000000#define plb1_acr_rdp_3deep 0x04000000#define plb1_acr_rdp_4deep 0x06000000#define plb1_acr_wrp_mask 0x01000000#define plb1_acr_wrp_disabled 0x00000000#define plb1_acr_wrp_2deep 0x01000000#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)/* Pin Function Control Register 1 */#define SDR0_PFC1 0x4101#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */⌨️ 快捷键说明
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