sa-1100.h

uboot详细解读可用启动引导LINUX2.6内核

#if LANGUAGE == C
#define RTAR				/* RTC Alarm Reg.		   */ \
			(*((volatile Word *) io_p2v (_RTAR)))
#define RCNR				/* RTC CouNt Reg.		   */ \
			(*((volatile Word *) io_p2v (_RCNR)))
#define RTTR				/* RTC Trim Reg.		   */ \
			(*((volatile Word *) io_p2v (_RTTR)))
#define RTSR				/* RTC Status Reg.		   */ \
			(*((volatile Word *) io_p2v (_RTSR)))
#endif /* LANGUAGE == C */

#define RTTR_C		Fld (16, 0)	/* clock divider Count - 1	   */
#define RTTR_D		Fld (10, 16)	/* trim Delete count		   */
					/* frtc = (1023*(C + 1) - D)*frtx/ */
					/*	  (1023*(C + 1)^2)	   */
					/* Trtc = (1023*(C + 1)^2)*Trtx/   */
					/*	  (1023*(C + 1) - D)	   */

#define RTSR_AL		0x00000001	/* ALarm detected		   */
#define RTSR_HZ		0x00000002	/* 1 Hz clock detected		   */
#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable	   */
#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable	   */


/*
 * Power Manager (PM) control registers
 *
 * Registers
 *    PMCR		Power Manager (PM) Control Register (read/write).
 *    PSSR		Power Manager (PM) Sleep Status Register (read/write).
 *    PSPR		Power Manager (PM) Scratch-Pad Register (read/write).
 *    PWER		Power Manager (PM) Wake-up Enable Register
 *			(read/write).
 *    PCFR		Power Manager (PM) general ConFiguration Register
 *			(read/write).
 *    PPCR		Power Manager (PM) Phase-Locked Loop (PLL)
 *			Configuration Register (read/write).
 *    PGSR		Power Manager (PM) General-Purpose Input/Output (GPIO)
 *			Sleep state Register (read/write, see GPIO pins).
 *    POSR		Power Manager (PM) Oscillator Status Register (read).
 *
 * Clocks
 *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
 *			or 3.5795 MHz).
 *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
 */

#define _PMCR		0x90020000	/* PM Control Reg.		   */
#define _PSSR		0x90020004	/* PM Sleep Status Reg.		   */
#define _PSPR		0x90020008	/* PM Scratch-Pad Reg.		   */
#define _PWER		0x9002000C	/* PM Wake-up Enable Reg.	   */
#define _PCFR		0x90020010	/* PM general ConFiguration Reg.   */
#define _PPCR		0x90020014	/* PM PLL Configuration Reg.	   */
#define _PGSR		0x90020018	/* PM GPIO Sleep state Reg.	   */
#define _POSR		0x9002001C	/* PM Oscillator Status Reg.	   */

#if LANGUAGE == C
#define PMCR				/* PM Control Reg.		   */ \
			(*((volatile Word *) io_p2v (_PMCR)))
#define PSSR				/* PM Sleep Status Reg.		   */ \
			(*((volatile Word *) io_p2v (_PSSR)))
#define PSPR				/* PM Scratch-Pad Reg.		   */ \
			(*((volatile Word *) io_p2v (_PSPR)))
#define PWER				/* PM Wake-up Enable Reg.	   */ \
			(*((volatile Word *) io_p2v (_PWER)))
#define PCFR				/* PM general ConFiguration Reg.   */ \
			(*((volatile Word *) io_p2v (_PCFR)))
#define PPCR				/* PM PLL Configuration Reg.	   */ \
			(*((volatile Word *) io_p2v (_PPCR)))
#define PGSR				/* PM GPIO Sleep state Reg.	   */ \
			(*((volatile Word *) io_p2v (_PGSR)))
#define POSR				/* PM Oscillator Status Reg.	   */ \
			(*((volatile Word *) io_p2v (_POSR)))

#elif LANGUAGE == Assembly
#define PMCR		(io_p2v (_PMCR))
#define PSSR		(io_p2v (_PSSR))
#define PSPR		(io_p2v (_PSPR))
#define PWER		(io_p2v (_PWER))
#define PCFR		(io_p2v (_PCFR))
#define PPCR		(io_p2v (_PPCR))
#define PGSR		(io_p2v (_PGSR))
#define POSR		(io_p2v (_POSR))

#endif /* LANGUAGE == C */

#define PMCR_SF		0x00000001	/* Sleep Force (set only)	   */

#define PSSR_SS		0x00000001	/* Software Sleep		   */
#define PSSR_BFS	0x00000002	/* Battery Fault Status		   */
					/* (BATT_FAULT)			   */
#define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */
#define PSSR_DH		0x00000008	/* DRAM control Hold		   */
#define PSSR_PH		0x00000010	/* Peripheral control Hold	   */

#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable	   */
#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable	   */
#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable	   */
#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable	   */
#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable	   */
#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable	   */
#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable	   */
#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable	   */
#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable	   */
#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable	   */
#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable	   */
#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable	   */
#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable	   */
#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable	   */
#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable	   */
#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable	   */
#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable	   */
#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable	   */
#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable	   */
#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable	   */
#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable	   */
#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable	   */
#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable	   */
#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable	   */
#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable	   */
#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable	   */
#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable	   */
#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable	   */
#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable	   */
#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable	   */

#define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */
#define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */
#define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */
#define PCFR_FP		0x00000002	/* Float PCMCIA pins		   */
#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)	   */
#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating	   */
#define PCFR_FS		0x00000004	/* Float Static memory pins	   */
#define PCFR_StMemNeg	(PCFR_FS*0)	/*  Static Memory pins Negated (1) */
#define PCFR_StMemFlt	(PCFR_FS*1)	/*  Static Memory pins Floating    */
#define PCFR_FO		0x00000008	/* Force RTC oscillator		   */
					/* (32.768 kHz) enable On	   */

#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.	   */
#define PPCR_Fx16			/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
			(0x00 << FShft (PPCR_CCF))
#define PPCR_Fx20			/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
			(0x01 << FShft (PPCR_CCF))
#define PPCR_Fx24			/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
			(0x02 << FShft (PPCR_CCF))
#define PPCR_Fx28			/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
			(0x03 << FShft (PPCR_CCF))
#define PPCR_Fx32			/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
			(0x04 << FShft (PPCR_CCF))
#define PPCR_Fx36			/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
			(0x05 << FShft (PPCR_CCF))
#define PPCR_Fx40			/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
			(0x06 << FShft (PPCR_CCF))
#define PPCR_Fx44			/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
			(0x07 << FShft (PPCR_CCF))
#define PPCR_Fx48			/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
			(0x08 << FShft (PPCR_CCF))
#define PPCR_Fx52			/*  Freq. x 52 (fcpu = 52*fxtl)    */ \
			(0x09 << FShft (PPCR_CCF))
#define PPCR_Fx56			/*  Freq. x 56 (fcpu = 56*fxtl)    */ \
			(0x0A << FShft (PPCR_CCF))
#define PPCR_Fx60			/*  Freq. x 60 (fcpu = 60*fxtl)    */ \
			(0x0B << FShft (PPCR_CCF))
#define PPCR_Fx64			/*  Freq. x 64 (fcpu = 64*fxtl)    */ \
			(0x0C << FShft (PPCR_CCF))
#define PPCR_Fx68			/*  Freq. x 68 (fcpu = 68*fxtl)    */ \
			(0x0D << FShft (PPCR_CCF))
#define PPCR_Fx72			/*  Freq. x 72 (fcpu = 72*fxtl)    */ \
			(0x0E << FShft (PPCR_CCF))
#define PPCR_Fx76			/*  Freq. x 76 (fcpu = 76*fxtl)    */ \
			(0x0F << FShft (PPCR_CCF))
					/*  3.6864 MHz crystal (fxtl):	   */
#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz	   */
#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz	   */
#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz	   */
#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz	   */
#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz	   */
#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz	   */
#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz	   */
#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz	   */
#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz	   */
#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz	   */
#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz	   */
#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz	   */
#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz	   */
#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz	   */
#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz	   */
#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz	   */
					/*  3.5795 MHz crystal (fxtl):	   */
#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz	   */
#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz	   */
#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz	   */
#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz	   */
#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz	   */
#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz	   */
#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz	   */
#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz	   */
#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz	   */
#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz	   */
#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz	   */
#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz	   */
#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz	   */
#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz	   */
#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz	   */
#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz	   */

#define POSR_OOK	0x00000001	/* RTC Oscillator (32.768 kHz) OK  */


/*
 * Reset Controller (RC) control registers
 *
 * Registers
 *    RSRR		Reset Controller (RC) Software Reset Register
 *			(read/write).
 *    RCSR		Reset Controller (RC) Status Register (read/write).
 */

#define _RSRR		0x90030000	/* RC Software Reset Reg.	   */
#define _RCSR		0x90030004	/* RC Status Reg.		   */

#if LANGUAGE == C
#define RSRR				/* RC Software Reset Reg.	   */ \
			(*((volatile Word *) io_p2v (_RSRR)))
#define RCSR				/* RC Status Reg.		   */ \
			(*((volatile Word *) io_p2v (_RCSR)))
#endif /* LANGUAGE == C */

#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)	   */

#define RCSR_HWR	0x00000001	/* HardWare Reset		   */
#define RCSR_SWR	0x00000002	/* SoftWare Reset		   */
#define RCSR_WDR	0x00000004	/* Watch-Dog Reset		   */
#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset		   */


/*
 * Test unit control registers
 *
 * Registers
 *    TUCR		Test Unit Control Register (read/write).
 */

#define _TUCR		0x90030008	/* Test Unit Control Reg.	   */

#if LANGUAGE == C
#define TUCR				/* Test Unit Control Reg.	   */ \
			(*((volatile Word *) io_p2v (_TUCR)))
#endif /* LANGUAGE == C */

#define TUCR_TIC	0x00000040	/* TIC mode			   */
#define TUCR_TTST	0x00000080	/* Trim TeST mode		   */
#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy	   */
					/* Check			   */
#define TUCR_PMD	0x00000200	/* Power Management Disable	   */
#define TUCR_MR		0x00000400	/* Memory Request mode		   */
#define TUCR_NoMB	(TUCR_MR*0)	/*  No Memory Bus request & grant  */
#define TUCR_MBGPIO	(TUCR_MR*1)	/*  Memory Bus request (MBREQ) &   */
					/*  grant (MBGNT) on GPIO [22:21]  */
#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits		   */
#define TUCR_FDC	0x00800000	/* RTC Force Delete Count	   */
#define TUCR_FMC	0x01000000	/* Force Michelle's Control mode   */
#define TUCR_TMC	0x02000000	/* RTC Trimmer Multiplexer Control */
#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep		   */
#define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */
#define TUCR_32_768kHz			/*  32.768 kHz osc. on GPIO [27]   */ \
			(0 << FShft (TUCR_TSEL))
#define TUCR_3_6864MHz			/*  3.6864 MHz osc. on GPIO [27]   */ \
			(1 << FShft (TUCR_TSEL))
#define TUCR_VDD			/*  VDD ring osc./16 on GPIO [27]  */ \
			(2 << FShft (TUCR_TSEL))
#define TUCR_96MHzPLL			/*  96 MHz PLL/4 on GPIO [27]	   */ \
			(3 << FShft (TUCR_TSEL))
#define TUCR_Clock			/*  internal (fcpu/2) & 32.768 kHz */ \
					/*  Clocks on GPIO [26:27]	   */ \
			(4 << FShft (TUCR_TSEL))
#define TUCR_3_6864MHzA			/*  3.6864 MHz osc. on GPIO [27]   */ \
					/*  (Alternative)		   */ \
			(5 << FShft (TUCR_TSEL))
#define TUCR_MainPLL			/*  Main PLL/16 on GPIO [27]	   */ \
			(6 << FShft (TUCR_TSEL))
#define TUCR_VDDL			/*  VDDL ring osc./4 on GPIO [27]  */ \
			(7 << FShft (TUCR_TSEL))


/*
 * General-Purpose Input/Output (GPIO) control registers
 *
 * Registers
 *    GPLR		General-Purpose Input/Output (GPIO) Pin Level
 *			Register (read).
 *    GPDR		General-Purpose Input/Output (GPIO) Pin Direction
 *			Register (read/write