sa-1100.h

uboot详细解读可用启动引导LINUX2.6内核

#define _Ser4MCCR1	0x90060030	/* Ser. port 4 MCP Control Reg. 1  */

#if LANGUAGE == C
#define Ser4MCCR0			/* Ser. port 4 MCP Control Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser4MCCR0)))
#define Ser4MCDR0			/* Ser. port 4 MCP Data Reg. 0	   */ \
					/* (audio)			   */ \
			(*((volatile Word *) io_p2v (_Ser4MCDR0)))
#define Ser4MCDR1			/* Ser. port 4 MCP Data Reg. 1	   */ \
					/* (telecom)			   */ \
			(*((volatile Word *) io_p2v (_Ser4MCDR1)))
#define Ser4MCDR2			/* Ser. port 4 MCP Data Reg. 2	   */ \
					/* (CODEC reg.)			   */ \
			(*((volatile Word *) io_p2v (_Ser4MCDR2)))
#define Ser4MCSR			/* Ser. port 4 MCP Status Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser4MCSR)))
#define Ser4MCCR1			/* Ser. port 4 MCP Control Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser4MCCR1)))
#endif /* LANGUAGE == C */

#define MCCR0_ASD	Fld (7, 0)	/* Audio Sampling rate Divisor/32  */
					/* [6..127]			   */
					/* faud = fmc/(32*ASD)		   */
					/* Taud = 32*ASD*Tmc		   */
#define MCCR0_AudSmpDiv(Div)		/*  Audio Sampling rate Divisor    */ \
					/*  [192..4064]			   */ \
			((Div)/32 << FShft (MCCR0_ASD))
					/*  faud = fmc/(32*Floor (Div/32)) */
					/*  Taud = 32*Floor (Div/32)*Tmc   */
#define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \
			(((Div) + 31)/32 << FShft (MCCR0_ASD))
					/*  faud = fmc/(32*Ceil (Div/32))  */
					/*  Taud = 32*Ceil (Div/32)*Tmc    */
#define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate	   */
					/* Divisor/32 [16..127]		   */
					/* ftcm = fmc/(32*TSD)		   */
					/* Ttcm = 32*TSD*Tmc		   */
#define MCCR0_TcmSmpDiv(Div)		/*  Telecom Sampling rate Divisor  */ \
					/*  [512..4064]			   */ \
			((Div)/32 << FShft (MCCR0_TSD))
					/*  ftcm = fmc/(32*Floor (Div/32)) */
					/*  Ttcm = 32*Floor (Div/32)*Tmc   */
#define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \
			(((Div) + 31)/32 << FShft (MCCR0_TSD))
					/*  ftcm = fmc/(32*Ceil (Div/32))  */
					/*  Ttcm = 32*Ceil (Div/32)*Tmc    */
#define MCCR0_MCE	0x00010000	/* MCP Enable			   */
#define MCCR0_ECS	0x00020000	/* External Clock Select	   */
#define MCCR0_IntClk	(MCCR0_ECS*0)	/*  Internal Clock (10 or 12 MHz)  */
#define MCCR0_ExtClk	(MCCR0_ECS*1)	/*  External Clock (GPIO [21])	   */
#define MCCR0_ADM	0x00040000	/* A/D (audio/telecom) data	   */
					/* sampling/storing Mode	   */
#define MCCR0_VldBit	(MCCR0_ADM*0)	/*  Valid Bit storing mode	   */
#define MCCR0_SmpCnt	(MCCR0_ADM*1)	/*  Sampling Counter storing mode  */
#define MCCR0_TTE	0x00080000	/* Telecom Transmit FIFO 1/2-full  */
					/* or less interrupt Enable	   */
#define MCCR0_TRE	0x00100000	/* Telecom Receive FIFO 1/2-full   */
					/* or more interrupt Enable	   */
#define MCCR0_ATE	0x00200000	/* Audio Transmit FIFO 1/2-full    */
					/* or less interrupt Enable	   */
#define MCCR0_ARE	0x00400000	/* Audio Receive FIFO 1/2-full or  */
					/* more interrupt Enable	   */
#define MCCR0_LBM	0x00800000	/* Look-Back Mode		   */
#define MCCR0_ECP	Fld (2, 24)	/* External Clock Prescaler - 1    */
#define MCCR0_ExtClkDiv(Div)		/*  External Clock Divisor [1..4]  */ \
			(((Div) - 1) << FShft (MCCR0_ECP))

#define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA	   */
					/* FIFOs			   */

#define MCDR1_DATA	Fld (14, 2)	/* receive/transmit telecom DATA   */
					/* FIFOs			   */

					/* receive/transmit CODEC reg.	   */
					/* FIFOs:			   */
#define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA			   */
#define MCDR2_RW	0x00010000	/*  reg. Read/Write (transmit)	   */
#define MCDR2_Rd	(MCDR2_RW*0)	/*   reg. Read			   */
#define MCDR2_Wr	(MCDR2_RW*1)	/*   reg. Write			   */
#define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress		   */

#define MCSR_ATS	0x00000001	/* Audio Transmit FIFO 1/2-full    */
					/* or less Service request (read)  */
#define MCSR_ARS	0x00000002	/* Audio Receive FIFO 1/2-full or  */
					/* more Service request (read)	   */
#define MCSR_TTS	0x00000004	/* Telecom Transmit FIFO 1/2-full  */
					/* or less Service request (read)  */
#define MCSR_TRS	0x00000008	/* Telecom Receive FIFO 1/2-full   */
					/* or more Service request (read)  */
#define MCSR_ATU	0x00000010	/* Audio Transmit FIFO Under-run   */
#define MCSR_ARO	0x00000020	/* Audio Receive FIFO Over-run	   */
#define MCSR_TTU	0x00000040	/* Telecom Transmit FIFO Under-run */
#define MCSR_TRO	0x00000080	/* Telecom Receive FIFO Over-run   */
#define MCSR_ANF	0x00000100	/* Audio transmit FIFO Not Full    */
					/* (read)			   */
#define MCSR_ANE	0x00000200	/* Audio receive FIFO Not Empty    */
					/* (read)			   */
#define MCSR_TNF	0x00000400	/* Telecom transmit FIFO Not Full  */
					/* (read)			   */
#define MCSR_TNE	0x00000800	/* Telecom receive FIFO Not Empty  */
					/* (read)			   */
#define MCSR_CWC	0x00001000	/* CODEC register Write Completed  */
					/* (read)			   */
#define MCSR_CRC	0x00002000	/* CODEC register Read Completed   */
					/* (read)			   */
#define MCSR_ACE	0x00004000	/* Audio CODEC Enabled (read)	   */
#define MCSR_TCE	0x00008000	/* Telecom CODEC Enabled (read)    */

#define MCCR1_CFS	0x00100000	/* Clock Freq. Select		   */
#define MCCR1_F12MHz	(MCCR1_CFS*0)	/*  Freq. (fmc) = ~ 12 MHz	   */
					/*  (11.981 MHz)		   */
#define MCCR1_F10MHz	(MCCR1_CFS*1)	/*  Freq. (fmc) = ~ 10 MHz	   */
					/*  (9.585 MHz)			   */


/*
 * Synchronous Serial Port (SSP) control registers
 *
 * Registers
 *    Ser4SSCR0		Serial port 4 Synchronous Serial Port (SSP) Control
 *			Register 0 (read/write).
 *    Ser4SSCR1		Serial port 4 Synchronous Serial Port (SSP) Control
 *			Register 1 (read/write).
 *			[Bits SPO and SP are only implemented in versions 2.0
 *			(rev. = 8) and higher of the StrongARM SA-1100.]
 *    Ser4SSDR		Serial port 4 Synchronous Serial Port (SSP) Data
 *			Register (read/write).
 *    Ser4SSSR		Serial port 4 Synchronous Serial Port (SSP) Status
 *			Register (read/write).
 *
 * Clocks
 *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
 *			or 3.5795 MHz).
 *    fss, Tss		Frequency, period of the SSP communication.
 */

#define _Ser4SSCR0	0x80070060	/* Ser. port 4 SSP Control Reg. 0  */
#define _Ser4SSCR1	0x80070064	/* Ser. port 4 SSP Control Reg. 1  */
#define _Ser4SSDR	0x8007006C	/* Ser. port 4 SSP Data Reg.	   */
#define _Ser4SSSR	0x80070074	/* Ser. port 4 SSP Status Reg.	   */

#if LANGUAGE == C
#define Ser4SSCR0			/* Ser. port 4 SSP Control Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser4SSCR0)))
#define Ser4SSCR1			/* Ser. port 4 SSP Control Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser4SSCR1)))
#define Ser4SSDR			/* Ser. port 4 SSP Data Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser4SSDR)))
#define Ser4SSSR			/* Ser. port 4 SSP Status Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser4SSSR)))
#endif /* LANGUAGE == C */

#define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */
#define SSCR0_DataSize(Size)		/*  Data Size Select [4..16]	   */ \
			(((Size) - 1) << FShft (SSCR0_DSS))
#define SSCR0_FRF	Fld (2, 4)	/* FRame Format			   */
#define SSCR0_Motorola			/*  Motorola Serial Peripheral	   */ \
					/*  Interface (SPI) format	   */ \
			(0 << FShft (SSCR0_FRF))
#define SSCR0_TI			/*  Texas Instruments Synchronous  */ \
					/*  Serial format		   */ \
			(1 << FShft (SSCR0_FRF))
#define SSCR0_National			/*  National Microwire format	   */ \
			(2 << FShft (SSCR0_FRF))
#define SSCR0_SSE	0x00000080	/* SSP Enable			   */
#define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */
					/* fss = fxtl/(2*(SCR + 1))	   */
					/* Tss = 2*(SCR + 1)*Txtl	   */
#define SSCR0_SerClkDiv(Div)		/*  Serial Clock Divisor [2..512]  */ \
			(((Div) - 2)/2 << FShft (SSCR0_SCR))
					/*  fss = fxtl/(2*Floor (Div/2))   */
					/*  Tss = 2*Floor (Div/2)*Txtl	   */
#define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \
			(((Div) - 1)/2 << FShft (SSCR0_SCR))
					/*  fss = fxtl/(2*Ceil (Div/2))    */
					/*  Tss = 2*Ceil (Div/2)*Txtl	   */

#define SSCR1_RIE	0x00000001	/* Receive FIFO 1/2-full or more   */
					/* Interrupt Enable		   */
#define SSCR1_TIE	0x00000002	/* Transmit FIFO 1/2-full or less  */
					/* Interrupt Enable		   */
#define SSCR1_LBM	0x00000004	/* Look-Back Mode		   */
#define SSCR1_SPO	0x00000008	/* Sample clock (SCLK) POlarity    */
#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low	   */
#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High	   */
#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase	   */
#define SSCR1_SClk1P	(SSCR1_SP*0)	/*  Sample Clock active 1 Period   */
					/*  after frame (SFRM, 1st edge)   */
#define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */
					/*  after frame (SFRM, 1st edge)   */
#define SSCR1_ECS	0x00000020	/* External Clock Select	   */
#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock		   */
#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])	   */

#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs	   */

#define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */
#define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
#define SSSR_BSY	0x00000008	/* SSP BuSY (read)		   */
#define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */
					/* Service request (read)	   */
#define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */
					/* Service request (read)	   */
#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run	   */


/*
 * Operating System (OS) timer control registers
 *
 * Registers
 *    OSMR0		Operating System (OS) timer Match Register 0
 *			(read/write).
 *    OSMR1		Operating System (OS) timer Match Register 1
 *			(read/write).
 *    OSMR2		Operating System (OS) timer Match Register 2
 *			(read/write).
 *    OSMR3		Operating System (OS) timer Match Register 3
 *			(read/write).
 *    OSCR		Operating System (OS) timer Counter Register
 *			(read/write).
 *    OSSR		Operating System (OS) timer Status Register
 *			(read/write).
 *    OWER		Operating System (OS) timer Watch-dog Enable Register
 *			(read/write).
 *    OIER		Operating System (OS) timer Interrupt Enable Register
 *			(read/write).
 */

#define _OSMR(Nb)			/* OS timer Match Reg. [0..3]	   */ \
			(0x90000000 + (Nb)*4)
#define _OSMR0		_OSMR (0)	/* OS timer Match Reg. 0	   */
#define _OSMR1		_OSMR (1)	/* OS timer Match Reg. 1	   */
#define _OSMR2		_OSMR (2)	/* OS timer Match Reg. 2	   */
#define _OSMR3		_OSMR (3)	/* OS timer Match Reg. 3	   */
#define _OSCR		0x90000010	/* OS timer Counter Reg.	   */
#define _OSSR		0x90000014	/* OS timer Status Reg.		   */
#define _OWER		0x90000018	/* OS timer Watch-dog Enable Reg.  */
#define _OIER		0x9000001C	/* OS timer Interrupt Enable Reg.  */

#if LANGUAGE == C
#define OSMR				/* OS timer Match Reg. [0..3]	   */ \
			((volatile Word *) io_p2v (_OSMR (0)))
#define OSMR0		(OSMR [0])	/* OS timer Match Reg. 0	   */
#define OSMR1		(OSMR [1])	/* OS timer Match Reg. 1	   */
#define OSMR2		(OSMR [2])	/* OS timer Match Reg. 2	   */
#define OSMR3		(OSMR [3])	/* OS timer Match Reg. 3	   */
#define OSCR				/* OS timer Counter Reg.	   */ \
			(*((volatile Word *) io_p2v (_OSCR)))
#define OSSR				/* OS timer Status Reg.		   */ \
			(*((volatile Word *) io_p2v (_OSSR)))
#define OWER				/* OS timer Watch-dog Enable Reg.  */ \
			(*((volatile Word *) io_p2v (_OWER)))
#define OIER				/* OS timer Interrupt Enable Reg.  */ \
			(*((volatile Word *) io_p2v (_OIER)))
#endif /* LANGUAGE == C */

#define OSSR_M(Nb)			/* Match detected [0..3]	   */ \
			(0x00000001 << (Nb))
#define OSSR_M0		OSSR_M (0)	/* Match detected 0		   */
#define OSSR_M1		OSSR_M (1)	/* Match detected 1		   */
#define OSSR_M2		OSSR_M (2)	/* Match detected 2		   */
#define OSSR_M3		OSSR_M (3)	/* Match detected 3		   */

#define OWER_WME	0x00000001	/* Watch-dog Match Enable	   */
					/* (set only)			   */

#define OIER_E(Nb)			/* match interrupt Enable [0..3]   */ \
			(0x00000001 << (Nb))
#define OIER_E0		OIER_E (0)	/* match interrupt Enable 0	   */
#define OIER_E1		OIER_E (1)	/* match interrupt Enable 1	   */
#define OIER_E2		OIER_E (2)	/* match interrupt Enable 2	   */
#define OIER_E3		OIER_E (3)	/* match interrupt Enable 3	   */


/*
 * Real-Time Clock (RTC) control registers
 *
 * Registers
 *    RTAR		Real-Time Clock (RTC) Alarm Register (read/write).
 *    RCNR		Real-Time Clock (RTC) CouNt Register (read/write).
 *    RTTR		Real-Time Clock (RTC) Trim Register (read/write).
 *    RTSR		Real-Time Clock (RTC) Status Register (read/write).
 *
 * Clocks
 *    frtx, Trtx	Frequency, period of the real-time clock crystal
 *			(32.768 kHz nominal).
 *    frtc, Trtc	Frequency, period of the real-time clock counter
 *			(1 Hz nominal).
 */

#define _RTAR		0x90010000	/* RTC Alarm Reg.		   */
#define _RCNR		0x90010004	/* RTC CouNt Reg.		   */
#define _RTTR		0x90010008	/* RTC Trim Reg.		   */
#define _RTSR		0x90010010	/* RTC Status Reg.		   */