sa-1100.h

uboot详细解读可用启动引导LINUX2.6内核

#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
#if 0					/* Hidden receive FIFO bits	   */
#define UTDR_PRE	0x00000100	/*  receive PaRity Error (read)    */
#define UTDR_FRE	0x00000200	/*  receive FRaming Error (read)   */
#define UTDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
#endif /* 0 */

#define UTSR0_TFS	0x00000001	/* Transmit FIFO 1/2-full or less  */
					/* Service request (read)	   */
#define UTSR0_RFS	0x00000002	/* Receive FIFO 1/3-to-2/3-full or */
					/* more Service request (read)	   */
#define UTSR0_RID	0x00000004	/* Receiver IDle		   */
#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break	   */
#define UTSR0_REB	0x00000010	/* Receive End of Break		   */
#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)		   */

#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)	   */
#define UTSR1_RNE	0x00000002	/* Receive FIFO Not Empty (read)   */
#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)	   */
#define UTSR1_FRE	0x00000010	/* receive FRaming Error (read)    */
#define UTSR1_ROR	0x00000020	/* Receive FIFO Over-Run (read)    */


/*
 * Synchronous Data Link Controller (SDLC) control registers
 *
 * Registers
 *    Ser1SDCR0		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Control Register 0 (read/write).
 *    Ser1SDCR1		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Control Register 1 (read/write).
 *    Ser1SDCR2		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Control Register 2 (read/write).
 *    Ser1SDCR3		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Control Register 3 (read/write).
 *    Ser1SDCR4		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Control Register 4 (read/write).
 *    Ser1SDDR		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Data Register (read/write).
 *    Ser1SDSR0		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Status Register 0 (read/write).
 *    Ser1SDSR1		Serial port 1 Synchronous Data Link Controller (SDLC)
 *			Status Register 1 (read/write).
 *
 * Clocks
 *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
 *			or 3.5795 MHz).
 *    fsd, Tsd		Frequency, period of the SDLC communication.
 */

#define _Ser1SDCR0	0x80020060	/* Ser. port 1 SDLC Control Reg. 0 */
#define _Ser1SDCR1	0x80020064	/* Ser. port 1 SDLC Control Reg. 1 */
#define _Ser1SDCR2	0x80020068	/* Ser. port 1 SDLC Control Reg. 2 */
#define _Ser1SDCR3	0x8002006C	/* Ser. port 1 SDLC Control Reg. 3 */
#define _Ser1SDCR4	0x80020070	/* Ser. port 1 SDLC Control Reg. 4 */
#define _Ser1SDDR	0x80020078	/* Ser. port 1 SDLC Data Reg.	   */
#define _Ser1SDSR0	0x80020080	/* Ser. port 1 SDLC Status Reg. 0  */
#define _Ser1SDSR1	0x80020084	/* Ser. port 1 SDLC Status Reg. 1  */

#if LANGUAGE == C
#define Ser1SDCR0			/* Ser. port 1 SDLC Control Reg. 0 */ \
			(*((volatile Word *) io_p2v (_Ser1SDCR0)))
#define Ser1SDCR1			/* Ser. port 1 SDLC Control Reg. 1 */ \
			(*((volatile Word *) io_p2v (_Ser1SDCR1)))
#define Ser1SDCR2			/* Ser. port 1 SDLC Control Reg. 2 */ \
			(*((volatile Word *) io_p2v (_Ser1SDCR2)))
#define Ser1SDCR3			/* Ser. port 1 SDLC Control Reg. 3 */ \
			(*((volatile Word *) io_p2v (_Ser1SDCR3)))
#define Ser1SDCR4			/* Ser. port 1 SDLC Control Reg. 4 */ \
			(*((volatile Word *) io_p2v (_Ser1SDCR4)))
#define Ser1SDDR			/* Ser. port 1 SDLC Data Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser1SDDR)))
#define Ser1SDSR0			/* Ser. port 1 SDLC Status Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser1SDSR0)))
#define Ser1SDSR1			/* Ser. port 1 SDLC Status Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser1SDSR1)))
#endif /* LANGUAGE == C */

#define SDCR0_SUS	0x00000001	/* SDLC/UART Select		   */
#define SDCR0_SDLC	(SDCR0_SUS*0)	/*  SDLC mode (TXD1 & RXD1)	   */
#define SDCR0_UART	(SDCR0_SUS*1)	/*  UART mode (TXD1 & RXD1)	   */
#define SDCR0_SDF	0x00000002	/* Single/Double start Flag select */
#define SDCR0_SglFlg	(SDCR0_SDF*0)	/*  Single start Flag		   */
#define SDCR0_DblFlg	(SDCR0_SDF*1)	/*  Double start Flag		   */
#define SDCR0_LBM	0x00000004	/* Look-Back Mode		   */
#define SDCR0_BMS	0x00000008	/* Bit Modulation Select	   */
#define SDCR0_FM0	(SDCR0_BMS*0)	/*  Freq. Modulation zero (0)	   */
#define SDCR0_NRZ	(SDCR0_BMS*1)	/*  Non-Return to Zero modulation  */
#define SDCR0_SCE	0x00000010	/* Sample Clock Enable (GPIO [16]) */
#define SDCR0_SCD	0x00000020	/* Sample Clock Direction select   */
					/* (GPIO [16])			   */
#define SDCR0_SClkIn	(SDCR0_SCD*0)	/*  Sample Clock Input		   */
#define SDCR0_SClkOut	(SDCR0_SCD*1)	/*  Sample Clock Output		   */
#define SDCR0_RCE	0x00000040	/* Receive Clock Edge select	   */
#define SDCR0_RcRsEdg	(SDCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
#define SDCR0_RcFlEdg	(SDCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
#define SDCR0_TCE	0x00000080	/* Transmit Clock Edge select	   */
#define SDCR0_TrRsEdg	(SDCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
#define SDCR0_TrFlEdg	(SDCR0_TCE*1)	/*  Transmit clock Falling-Edge    */

#define SDCR1_AAF	0x00000001	/* Abort After Frame enable	   */
					/* (GPIO [17])			   */
#define SDCR1_TXE	0x00000002	/* Transmit Enable		   */
#define SDCR1_RXE	0x00000004	/* Receive Enable		   */
#define SDCR1_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
					/* more Interrupt Enable	   */
#define SDCR1_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
					/* Interrupt Enable		   */
#define SDCR1_AME	0x00000020	/* Address Match Enable		   */
#define SDCR1_TUS	0x00000040	/* Transmit FIFO Under-run Select  */
#define SDCR1_EFrmURn	(SDCR1_TUS*0)	/*  End Frame on Under-Run	   */
#define SDCR1_AbortURn	(SDCR1_TUS*1)	/*  Abort on Under-Run		   */
#define SDCR1_RAE	0x00000080	/* Receive Abort interrupt Enable  */

#define SDCR2_AMV	Fld (8, 0)	/* Address Match Value		   */

#define SDCR3_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
#define SDCR4_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
					/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
					/* Tsd = 16*(BRD[11:0] + 1)*Txtl   */
#define SDCR3_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
			(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
			 FShft (SDCR3_BRD))
#define SDCR4_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
			(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
			 FShft (SDCR4_BRD))
					/*  fsd = fxtl/(16*Floor (Div/16)) */
					/*  Tsd = 16*Floor (Div/16)*Txtl   */
#define SDCR3_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
			(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
			 FShft (SDCR3_BRD))
#define SDCR4_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
			(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
			 FShft (SDCR4_BRD))
					/*  fsd = fxtl/(16*Ceil (Div/16))  */
					/*  Tsd = 16*Ceil (Div/16)*Txtl    */

#define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
#if 0					/* Hidden receive FIFO bits	   */
#define SDDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
#define SDDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
#define SDDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
#endif /* 0 */

#define SDSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
#define SDSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
#define SDSR0_RAB	0x00000004	/* Receive ABort		   */
#define SDSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
					/* Service request (read)	   */
#define SDSR0_RFS	0x00000010	/* Receive FIFO 1/3-to-2/3-full or */
					/* more Service request (read)	   */

#define SDSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
#define SDSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
#define SDSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
#define SDSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
#define SDSR1_RTD	0x00000010	/* Receive Transition Detected	   */
#define SDSR1_EOF	0x00000020	/* receive End-Of-Frame (read)	   */
#define SDSR1_CRE	0x00000040	/* receive CRC Error (read)	   */
#define SDSR1_ROR	0x00000080	/* Receive FIFO Over-Run (read)    */


/*
 * High-Speed Serial to Parallel controller (HSSP) control registers
 *
 * Registers
 *    Ser2HSCR0		Serial port 2 High-Speed Serial to Parallel
 *			controller (HSSP) Control Register 0 (read/write).
 *    Ser2HSCR1		Serial port 2 High-Speed Serial to Parallel
 *			controller (HSSP) Control Register 1 (read/write).
 *    Ser2HSDR		Serial port 2 High-Speed Serial to Parallel
 *			controller (HSSP) Data Register (read/write).
 *    Ser2HSSR0		Serial port 2 High-Speed Serial to Parallel
 *			controller (HSSP) Status Register 0 (read/write).
 *    Ser2HSSR1		Serial port 2 High-Speed Serial to Parallel
 *			controller (HSSP) Status Register 1 (read).
 *    Ser2HSCR2		Serial port 2 High-Speed Serial to Parallel
 *			controller (HSSP) Control Register 2 (read/write).
 *			[The HSCR2 register is only implemented in
 *			versions 2.0 (rev. = 8) and higher of the StrongARM
 *			SA-1100.]
 */

#define _Ser2HSCR0	0x80040060	/* Ser. port 2 HSSP Control Reg. 0 */
#define _Ser2HSCR1	0x80040064	/* Ser. port 2 HSSP Control Reg. 1 */
#define _Ser2HSDR	0x8004006C	/* Ser. port 2 HSSP Data Reg.	   */
#define _Ser2HSSR0	0x80040074	/* Ser. port 2 HSSP Status Reg. 0  */
#define _Ser2HSSR1	0x80040078	/* Ser. port 2 HSSP Status Reg. 1  */
#define _Ser2HSCR2	0x90060028	/* Ser. port 2 HSSP Control Reg. 2 */

#if LANGUAGE == C
#define Ser2HSCR0			/* Ser. port 2 HSSP Control Reg. 0 */ \
			(*((volatile Word *) io_p2v (_Ser2HSCR0)))
#define Ser2HSCR1			/* Ser. port 2 HSSP Control Reg. 1 */ \
			(*((volatile Word *) io_p2v (_Ser2HSCR1)))
#define Ser2HSDR			/* Ser. port 2 HSSP Data Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser2HSDR)))
#define Ser2HSSR0			/* Ser. port 2 HSSP Status Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser2HSSR0)))
#define Ser2HSSR1			/* Ser. port 2 HSSP Status Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser2HSSR1)))
#define Ser2HSCR2			/* Ser. port 2 HSSP Control Reg. 2 */ \
			(*((volatile Word *) io_p2v (_Ser2HSCR2)))
#endif /* LANGUAGE == C */

#define HSCR0_ITR	0x00000001	/* IrDA Transmission Rate	   */
#define HSCR0_UART	(HSCR0_ITR*0)	/*  UART mode (115.2 kb/s if IrDA) */
#define HSCR0_HSSP	(HSCR0_ITR*1)	/*  HSSP mode (4 Mb/s)		   */
#define HSCR0_LBM	0x00000002	/* Look-Back Mode		   */
#define HSCR0_TUS	0x00000004	/* Transmit FIFO Under-run Select  */
#define HSCR0_EFrmURn	(HSCR0_TUS*0)	/*  End Frame on Under-Run	   */
#define HSCR0_AbortURn	(HSCR0_TUS*1)	/*  Abort on Under-Run		   */
#define HSCR0_TXE	0x00000008	/* Transmit Enable		   */
#define HSCR0_RXE	0x00000010	/* Receive Enable		   */
#define HSCR0_RIE	0x00000020	/* Receive FIFO 2/5-to-3/5-full or */
					/* more Interrupt Enable	   */
#define HSCR0_TIE	0x00000040	/* Transmit FIFO 1/2-full or less  */
					/* Interrupt Enable		   */
#define HSCR0_AME	0x00000080	/* Address Match Enable		   */

#define HSCR1_AMV	Fld (8, 0)	/* Address Match Value		   */

#define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
#if 0					/* Hidden receive FIFO bits	   */
#define HSDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
#define HSDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
#define HSDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
#endif /* 0 */

#define HSSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
#define HSSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
#define HSSR0_RAB	0x00000004	/* Receive ABort		   */
#define HSSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
					/* Service request (read)	   */
#define HSSR0_RFS	0x00000010	/* Receive FIFO 2/5-to-3/5-full or */
					/* more Service request (read)	   */
#define HSSR0_FRE	0x00000020	/* receive FRaming Error	   */

#define HSSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
#define HSSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
#define HSSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
#define HSSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
#define HSSR1_EOF	0x00000010	/* receive End-Of-Frame (read)	   */
#define HSSR1_CRE	0x00000020	/* receive CRC Error (read)	   */
#define HSSR1_ROR	0x00000040	/* Receive FIFO Over-Run (read)    */

#define HSCR2_TXP	0x00040000	/* Transmit data Polarity (TXD_2)  */
#define HSCR2_TrDataL	(HSCR2_TXP*0)	/*  Transmit Data active Low	   */
					/*  (inverted)			   */
#define HSCR2_TrDataH	(HSCR2_TXP*1)	/*  Transmit Data active High	   */
					/*  (non-inverted)		   */
#define HSCR2_RXP	0x00080000	/* Receive data Polarity (RXD_2)   */
#define HSCR2_RcDataL	(HSCR2_RXP*0)	/*  Receive Data active Low	   */
					/*  (inverted)			   */
#define HSCR2_RcDataH	(HSCR2_RXP*1)	/*  Receive Data active High	   */
					/*  (non-inverted)		   */


/*
 * Multi-media Communications Port (MCP) control registers
 *
 * Registers
 *    Ser4MCCR0		Serial port 4 Multi-media Communications Port (MCP)
 *			Control Register 0 (read/write).
 *    Ser4MCDR0		Serial port 4 Multi-media Communications Port (MCP)
 *			Data Register 0 (audio, read/write).
 *    Ser4MCDR1		Serial port 4 Multi-media Communications Port (MCP)
 *			Data Register 1 (telecom, read/write).
 *    Ser4MCDR2		Serial port 4 Multi-media Communications Port (MCP)
 *			Data Register 2 (CODEC registers, read/write).
 *    Ser4MCSR		Serial port 4 Multi-media Communications Port (MCP)
 *			Status Register (read/write).
 *    Ser4MCCR1		Serial port 4 Multi-media Communications Port (MCP)
 *			Control Register 1 (read/write).
 *			[The MCCR1 register is only implemented in
 *			versions 2.0 (rev. = 8) and higher of the StrongARM
 *			SA-1100.]
 *
 * Clocks
 *    fmc, Tmc		Frequency, period of the MCP communication (10 MHz,
 *			12 MHz, or GPIO [21]).
 *    faud, Taud	Frequency, period of the audio sampling.
 *    ftcm, Ttcm	Frequency, period of the telecom sampling.
 */

#define _Ser4MCCR0	0x80060000	/* Ser. port 4 MCP Control Reg. 0  */
#define _Ser4MCDR0	0x80060008	/* Ser. port 4 MCP Data Reg. 0	   */
					/* (audio)			   */
#define _Ser4MCDR1	0x8006000C	/* Ser. port 4 MCP Data Reg. 1	   */
					/* (telecom)			   */
#define _Ser4MCDR2	0x80060010	/* Ser. port 4 MCP Data Reg. 2	   */
					/* (CODEC reg.)			   */
#define _Ser4MCSR	0x80060018	/* Ser. port 4 MCP Status Reg.	   */