sa-1100.h

uboot详细解读可用启动引导LINUX2.6内核

#define UDCCS0_SST	0x00000004	/* Sent STall			   */
#define UDCCS0_FST	0x00000008	/* Force STall			   */
#define UDCCS0_DE	0x00000010	/* Data End			   */
#define UDCCS0_SE	0x00000020	/* Setup End (read)		   */
#define UDCCS0_SO	0x00000040	/* Serviced Output packet ready    */
					/* (write)			   */
#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)	   */

#define UDCCS1_RFS	0x00000001	/* Receive FIFO 12-bytes or more   */
					/* Service request (read)	   */
#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete	   */
#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)	   */
#define UDCCS1_SST	0x00000008	/* Sent STall			   */
#define UDCCS1_FST	0x00000010	/* Force STall			   */
#define UDCCS1_RNE	0x00000020	/* Receive FIFO Not Empty (read)   */

#define UDCCS2_TFS	0x00000001	/* Transmit FIFO 8-bytes or less   */
					/* Service request (read)	   */
#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete	   */
#define UDCCS2_TPE	0x00000004	/* Transmit Packet Error (read)    */
#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run	   */
#define UDCCS2_SST	0x00000010	/* Sent STall			   */
#define UDCCS2_FST	0x00000020	/* Force STall			   */

#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */

#define UDCWC_WC	Fld (4, 0)	/* Write Count			   */

#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */

#define UDCSR_EIR	0x00000001	/* End-point 0 Interrupt Request   */
#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request	   */
#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request	   */
#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request	   */
#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request	   */
#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request	   */


/*
 * Universal Asynchronous Receiver/Transmitter (UART) control registers
 *
 * Registers
 *    Ser1UTCR0		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 0
 *			(read/write).
 *    Ser1UTCR1		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 1
 *			(read/write).
 *    Ser1UTCR2		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 2
 *			(read/write).
 *    Ser1UTCR3		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 3
 *			(read/write).
 *    Ser1UTDR		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Data Register
 *			(read/write).
 *    Ser1UTSR0		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Status Register 0
 *			(read/write).
 *    Ser1UTSR1		Serial port 1 Universal Asynchronous
 *			Receiver/Transmitter (UART) Status Register 1 (read).
 *
 *    Ser2UTCR0		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 0
 *			(read/write).
 *    Ser2UTCR1		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 1
 *			(read/write).
 *    Ser2UTCR2		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 2
 *			(read/write).
 *    Ser2UTCR3		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 3
 *			(read/write).
 *    Ser2UTCR4		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 4
 *			(read/write).
 *    Ser2UTDR		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Data Register
 *			(read/write).
 *    Ser2UTSR0		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Status Register 0
 *			(read/write).
 *    Ser2UTSR1		Serial port 2 Universal Asynchronous
 *			Receiver/Transmitter (UART) Status Register 1 (read).
 *
 *    Ser3UTCR0		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 0
 *			(read/write).
 *    Ser3UTCR1		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 1
 *			(read/write).
 *    Ser3UTCR2		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 2
 *			(read/write).
 *    Ser3UTCR3		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Control Register 3
 *			(read/write).
 *    Ser3UTDR		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Data Register
 *			(read/write).
 *    Ser3UTSR0		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Status Register 0
 *			(read/write).
 *    Ser3UTSR1		Serial port 3 Universal Asynchronous
 *			Receiver/Transmitter (UART) Status Register 1 (read).
 *
 * Clocks
 *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
 *			or 3.5795 MHz).
 *    fua, Tua		Frequency, period of the UART communication.
 */

#define _UTCR0(Nb)			/* UART Control Reg. 0 [1..3]	   */ \
			(0x80010000 + ((Nb) - 1)*0x00020000)
#define _UTCR1(Nb)			/* UART Control Reg. 1 [1..3]	   */ \
			(0x80010004 + ((Nb) - 1)*0x00020000)
#define _UTCR2(Nb)			/* UART Control Reg. 2 [1..3]	   */ \
			(0x80010008 + ((Nb) - 1)*0x00020000)
#define _UTCR3(Nb)			/* UART Control Reg. 3 [1..3]	   */ \
			(0x8001000C + ((Nb) - 1)*0x00020000)
#define _UTCR4(Nb)			/* UART Control Reg. 4 [2]	   */ \
			(0x80010010 + ((Nb) - 1)*0x00020000)
#define _UTDR(Nb)			/* UART Data Reg. [1..3]	   */ \
			(0x80010014 + ((Nb) - 1)*0x00020000)
#define _UTSR0(Nb)			/* UART Status Reg. 0 [1..3]	   */ \
			(0x8001001C + ((Nb) - 1)*0x00020000)
#define _UTSR1(Nb)			/* UART Status Reg. 1 [1..3]	   */ \
			(0x80010020 + ((Nb) - 1)*0x00020000)

#define _Ser1UTCR0	_UTCR0 (1)	/* Ser. port 1 UART Control Reg. 0 */
#define _Ser1UTCR1	_UTCR1 (1)	/* Ser. port 1 UART Control Reg. 1 */
#define _Ser1UTCR2	_UTCR2 (1)	/* Ser. port 1 UART Control Reg. 2 */
#define _Ser1UTCR3	_UTCR3 (1)	/* Ser. port 1 UART Control Reg. 3 */
#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.	   */
#define _Ser1UTSR0	_UTSR0 (1)	/* Ser. port 1 UART Status Reg. 0  */
#define _Ser1UTSR1	_UTSR1 (1)	/* Ser. port 1 UART Status Reg. 1  */

#define _Ser2UTCR0	_UTCR0 (2)	/* Ser. port 2 UART Control Reg. 0 */
#define _Ser2UTCR1	_UTCR1 (2)	/* Ser. port 2 UART Control Reg. 1 */
#define _Ser2UTCR2	_UTCR2 (2)	/* Ser. port 2 UART Control Reg. 2 */
#define _Ser2UTCR3	_UTCR3 (2)	/* Ser. port 2 UART Control Reg. 3 */
#define _Ser2UTCR4	_UTCR4 (2)	/* Ser. port 2 UART Control Reg. 4 */
#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.	   */
#define _Ser2UTSR0	_UTSR0 (2)	/* Ser. port 2 UART Status Reg. 0  */
#define _Ser2UTSR1	_UTSR1 (2)	/* Ser. port 2 UART Status Reg. 1  */

#define _Ser3UTCR0	_UTCR0 (3)	/* Ser. port 3 UART Control Reg. 0 */
#define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
#define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
#define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.	   */
#define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
#define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */

#if LANGUAGE == C

#define Ser1UTCR0			/* Ser. port 1 UART Control Reg. 0 */ \
			(*((volatile Word *) io_p2v (_Ser1UTCR0)))
#define Ser1UTCR1			/* Ser. port 1 UART Control Reg. 1 */ \
			(*((volatile Word *) io_p2v (_Ser1UTCR1)))
#define Ser1UTCR2			/* Ser. port 1 UART Control Reg. 2 */ \
			(*((volatile Word *) io_p2v (_Ser1UTCR2)))
#define Ser1UTCR3			/* Ser. port 1 UART Control Reg. 3 */ \
			(*((volatile Word *) io_p2v (_Ser1UTCR3)))
#define Ser1UTDR			/* Ser. port 1 UART Data Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser1UTDR)))
#define Ser1UTSR0			/* Ser. port 1 UART Status Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser1UTSR0)))
#define Ser1UTSR1			/* Ser. port 1 UART Status Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser1UTSR1)))

#define Ser2UTCR0			/* Ser. port 2 UART Control Reg. 0 */ \
			(*((volatile Word *) io_p2v (_Ser2UTCR0)))
#define Ser2UTCR1			/* Ser. port 2 UART Control Reg. 1 */ \
			(*((volatile Word *) io_p2v (_Ser2UTCR1)))
#define Ser2UTCR2			/* Ser. port 2 UART Control Reg. 2 */ \
			(*((volatile Word *) io_p2v (_Ser2UTCR2)))
#define Ser2UTCR3			/* Ser. port 2 UART Control Reg. 3 */ \
			(*((volatile Word *) io_p2v (_Ser2UTCR3)))
#define Ser2UTCR4			/* Ser. port 2 UART Control Reg. 4 */ \
			(*((volatile Word *) io_p2v (_Ser2UTCR4)))
#define Ser2UTDR			/* Ser. port 2 UART Data Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser2UTDR)))
#define Ser2UTSR0			/* Ser. port 2 UART Status Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser2UTSR0)))
#define Ser2UTSR1			/* Ser. port 2 UART Status Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser2UTSR1)))

#define Ser3UTCR0			/* Ser. port 3 UART Control Reg. 0 */ \
			(*((volatile Word *) io_p2v (_Ser3UTCR0)))
#define Ser3UTCR1			/* Ser. port 3 UART Control Reg. 1 */ \
			(*((volatile Word *) io_p2v (_Ser3UTCR1)))
#define Ser3UTCR2			/* Ser. port 3 UART Control Reg. 2 */ \
			(*((volatile Word *) io_p2v (_Ser3UTCR2)))
#define Ser3UTCR3			/* Ser. port 3 UART Control Reg. 3 */ \
			(*((volatile Word *) io_p2v (_Ser3UTCR3)))
#define Ser3UTDR			/* Ser. port 3 UART Data Reg.	   */ \
			(*((volatile Word *) io_p2v (_Ser3UTDR)))
#define Ser3UTSR0			/* Ser. port 3 UART Status Reg. 0  */ \
			(*((volatile Word *) io_p2v (_Ser3UTSR0)))
#define Ser3UTSR1			/* Ser. port 3 UART Status Reg. 1  */ \
			(*((volatile Word *) io_p2v (_Ser3UTSR1)))

#elif LANGUAGE == Assembly
#define Ser1UTCR0	( io_p2v (_Ser1UTCR0))
#define Ser1UTCR1	( io_p2v (_Ser1UTCR1))
#define Ser1UTCR2	( io_p2v (_Ser1UTCR2))
#define Ser1UTCR3	( io_p2v (_Ser1UTCR3))
#define Ser1UTDR	( io_p2v (_Ser1UTDR))
#define Ser1UTSR0	( io_p2v (_Ser1UTSR0))
#define Ser1UTSR1	( io_p2v (_Ser1UTSR1))

#define Ser2UTCR0	( io_p2v (_Ser2UTCR0))
#define Ser2UTCR1	( io_p2v (_Ser2UTCR1))
#define Ser2UTCR2	( io_p2v (_Ser2UTCR2))
#define Ser2UTCR3	( io_p2v (_Ser2UTCR3))
#define Ser2UTCR4	( io_p2v (_Ser2UTCR4))
#define Ser2UTDR	( io_p2v (_Ser2UTDR))
#define Ser2UTSR0	( io_p2v (_Ser2UTSR0))
#define Ser2UTSR1	( io_p2v (_Ser2UTSR1))

#define Ser3UTCR0	( io_p2v (_Ser3UTCR0))
#define Ser3UTCR1	( io_p2v (_Ser3UTCR1))
#define Ser3UTCR2	( io_p2v (_Ser3UTCR2))
#define Ser3UTCR3	( io_p2v (_Ser3UTCR3))
#define Ser3UTDR	( io_p2v (_Ser3UTDR))
#define Ser3UTSR0	( io_p2v (_Ser3UTSR0))
#define Ser3UTSR1	( io_p2v (_Ser3UTSR1))

#endif /* LANGUAGE == C */

#define UTCR0_PE	0x00000001	/* Parity Enable		   */
#define UTCR0_OES	0x00000002	/* Odd/Even parity Select	   */
#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity			   */
#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity			   */
#define UTCR0_SBS	0x00000004	/* Stop Bit Select		   */
#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame	   */
#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame	   */
#define UTCR0_DSS	0x00000008	/* Data Size Select		   */
#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data			   */
#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data			   */
#define UTCR0_SCE	0x00000010	/* Sample Clock Enable		   */
					/* (ser. port 1: GPIO [18],	   */
					/* ser. port 3: GPIO [20])	   */
#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select	   */
#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select	   */
#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
#define UTCR0_TrFlEdg	(UTCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
#define UTCR0_Ser2IrDA			/* Ser. port 2 IrDA settings	   */ \
			(UTCR0_1StpBit + UTCR0_8BitData)

#define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
#define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
					/* fua = fxtl/(16*(BRD[11:0] + 1)) */
					/* Tua = 16*(BRD [11:0] + 1)*Txtl  */
#define UTCR1_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
			(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
			 FShft (UTCR1_BRD))
#define UTCR2_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
			(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
			 FShft (UTCR2_BRD))
					/*  fua = fxtl/(16*Floor (Div/16)) */
					/*  Tua = 16*Floor (Div/16)*Txtl   */
#define UTCR1_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
			(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
			 FShft (UTCR1_BRD))
#define UTCR2_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
			(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
			 FShft (UTCR2_BRD))
					/*  fua = fxtl/(16*Ceil (Div/16))  */
					/*  Tua = 16*Ceil (Div/16)*Txtl    */

#define UTCR3_RXE	0x00000001	/* Receive Enable		   */
#define UTCR3_TXE	0x00000002	/* Transmit Enable		   */
#define UTCR3_BRK	0x00000004	/* BReaK mode			   */
#define UTCR3_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
					/* more Interrupt Enable	   */
#define UTCR3_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
					/* Interrupt Enable		   */
#define UTCR3_LBM	0x00000020	/* Look-Back Mode		   */
#define UTCR3_Ser2IrDA			/* Ser. port 2 IrDA settings (RIE, */ \
					/* TIE, LBM can be set or cleared) */ \
			(UTCR3_RXE + UTCR3_TXE)

#define UTCR4_HSE	0x00000001	/* Hewlett-Packard Serial InfraRed */
					/* (HP-SIR) modulation Enable	   */
#define UTCR4_NRZ	(UTCR4_HSE*0)	/*  Non-Return to Zero modulation  */
#define UTCR4_HPSIR	(UTCR4_HSE*1)	/*  HP-SIR modulation		   */
#define UTCR4_LPM	0x00000002	/* Low-Power Mode		   */
#define UTCR4_Z3_16Bit	(UTCR4_LPM*0)	/*  Zero pulse = 3/16 Bit time	   */
#define UTCR4_Z1_6us	(UTCR4_LPM*1)	/*  Zero pulse = 1.6 us		   */