sc520.h

uboot详细解读可用启动引导LINUX2.6内核

#define SC520_GP9IMAP		0x0d59	/* GPIRQ9 Interrupt Mapping Register */
#define SC520_GP10IMAP		0x0d5a	/* GPIRQ10 Interrupt Mapping Register */
#define SC520_SYSINFO		0x0d70	/* System Board Information Register */
#define SC520_RESCFG		0x0d72	/* Reset Configuration Register */
#define SC520_RESSTA		0x0d74	/* Reset Status Register */
#define SC520_GPDMAMMIO		0x0d81	/* GP-DMA Memory-Mapped I/O Register */
#define SC520_GPDMAEXTCHMAPA	0x0d82	/* GP-DMA Resource Channel Map A */
#define SC520_GPDMAEXTCHMAPB	0x0d84	/* GP-DMA Resource Channel Map B */
#define SC520_GPDMAEXTPG0	0x0d86	/* GP-DMA Channel 0 Extended Page */
#define SC520_GPDMAEXTPG1	0x0d87	/* GP-DMA Channel 1 Extended Page */
#define SC520_GPDMAEXTPG2	0x0d88	/* GP-DMA Channel 2 Extended Page */
#define SC520_GPDMAEXTPG3	0x0d89	/* GP-DMA Channel 3 Extended Page */
#define SC520_GPDMAEXTPG5	0x0d8a	/* GP-DMA Channel 5 Extended Page */
#define SC520_GPDMAEXTPG6	0x0d8b	/* GP-DMA Channel 6 Extended Page */
#define SC520_GPDMAEXTPG7	0x0d8c	/* GP-DMA Channel 7 Extended Page */
#define SC520_GPDMAEXTTC3	0x0d90	/* GP-DMA Channel 3 Extender Transfer count */
#define SC520_GPDMAEXTTC5	0x0d91	/* GP-DMA Channel 5 Extender Transfer count */
#define SC520_GPDMAEXTTC6	0x0d92	/* GP-DMA Channel 6 Extender Transfer count */
#define SC520_GPDMAEXTTC7	0x0d93	/* GP-DMA Channel 7 Extender Transfer count */
#define SC520_GPDMABCCTL	0x0d98	/* Buffer Chaining Control */
#define SC520_GPDMABCSTA	0x0d99	/* Buffer Chaining Status */
#define SC520_GPDMABSINTENB	0x0d9a	/* Buffer Chaining Interrupt Enable */
#define SC520_GPDMABCVAL	0x0d9b	/* Buffer Chaining Valid */
#define SC520_GPDMANXTADDL3	0x0da0	/* GP-DMA Channel 3 Next Address Low */
#define SC520_GPDMANXTADDH3	0x0da2	/* GP-DMA Channel 3 Next Address High */
#define SC520_GPDMANXTADDL5	0x0da4	/* GP-DMA Channel 5 Next Address Low */
#define SC520_GPDMANXTADDH5	0x0da6	/* GP-DMA Channel 5 Next Address High */
#define SC520_GPDMANXTADDL6	0x0da8	/* GP-DMA Channel 6 Next Address Low */
#define SC520_GPDMANXTADDH6	0x0daa	/* GP-DMA Channel 6 Next Address High */
#define SC520_GPDMANXTADDL7	0x0dac	/* GP-DMA Channel 7 Next Address Low */
#define SC520_GPDMANXTADDH7	0x0dae	/* GP-DMA Channel 7 Next Address High */
#define SC520_GPDMANXTTCL3	0x0db0	/* GP-DMA Channel 3 Next Transfer Count Low */
#define SC520_GPDMANXTTCH3	0x0db2	/* GP-DMA Channel 3 Next Transfer Count High */
#define SC520_GPDMANXTTCL5	0x0db4	/* GP-DMA Channel 5 Next Transfer Count Low */
#define SC520_GPDMANXTTCH5	0x0db6	/* GP-DMA Channel 5 Next Transfer Count High */
#define SC520_GPDMANXTTCL6	0x0db8	/* GP-DMA Channel 6 Next Transfer Count Low */
#define SC520_GPDMANXTTCH6	0x0dba	/* GP-DMA Channel 6 Next Transfer Count High */
#define SC520_GPDMANXTTCL7	0x0dbc	/* GP-DMA Channel 7 Next Transfer Count Low */
#define SC520_GPDMANXTTCH7	0x0dbe	/* GP-DMA Channel 7 Next Transfer Count High */

/* MMCR Register bits (not all of them :) ) */

/* SSI Stuff */
#define CTL_CLK_SEL_4		0x00	/* Nominal Bit Rate = 8 MHz    */
#define CTL_CLK_SEL_8		0x10	/* Nominal Bit Rate = 4 MHz    */
#define CTL_CLK_SEL_16		0x20	/* Nominal Bit Rate = 2 MHz    */
#define CTL_CLK_SEL_32		0x30	/* Nominal Bit Rate = 1 MHz    */
#define CTL_CLK_SEL_64		0x40	/* Nominal Bit Rate = 512 KHz  */
#define CTL_CLK_SEL_128		0x50	/* Nominal Bit Rate = 256 KHz  */
#define CTL_CLK_SEL_256		0x60	/* Nominal Bit Rate = 128 KHz  */
#define CTL_CLK_SEL_512		0x70	/* Nominal Bit Rate = 64 KHz   */

#define TC_INT_ENB		0x08	/* Transaction Complete Interrupt Enable */
#define PHS_INV_ENB		0x04	/* SSI Inverted Phase Mode Enable */
#define CLK_INV_ENB		0x02	/* SSI Inverted Clock Mode Enable */
#define MSBF_ENB		0x01	/* SSI Most Significant Bit First Mode Enable */

#define SSICMD_CMD_SEL_XMITRCV	0x03	/* Simultaneous Transmit / Receive Transaction */
#define SSICMD_CMD_SEL_RCV	0x02	/* Receive Transaction */
#define SSICMD_CMD_SEL_XMIT	0x01	/* Transmit Transaction */
#define SSISTA_BSY		0x02	/* SSI Busy */
#define SSISTA_TC_INT		0x01	/* SSI Transaction Complete Interrupt */


/* BITS for SC520_ADDDECCTL: */
#define WPV_INT_ENB		0x80	/* Write-Protect Violation Interrupt Enable */
#define IO_HOLE_DEST_PCI	0x10	/* I/O Hole Access Destination */
#define RTC_DIS			0x04	/* RTC Disable */
#define UART2_DIS		0x02	/* UART2 Disable */
#define UART1_DIS		0x01	/* UART1 Disable */

/* bus mapping constants (used for PCI core initialization) */																																																 /* bus mapping constants */
#define SC520_REG_ADDR		0x00000cf8
#define SC520_REG_DATA		0x00000cfc


#define SC520_ISA_MEM_PHYS	0x00000000
#define SC520_ISA_MEM_BUS	0x00000000
#define SC520_ISA_MEM_SIZE	0x01000000

#define SC520_ISA_IO_PHYS	0x00000000
#define SC520_ISA_IO_BUS	0x00000000
#define SC520_ISA_IO_SIZE	0x00001000

/* PCI I/O space from 0x1000 to 0xdfff
 * (make 0xe000-0xfdff available for stuff like PCCard boot) */
#define SC520_PCI_IO_PHYS	0x00001000
#define SC520_PCI_IO_BUS	0x00001000
#define SC520_PCI_IO_SIZE	0x0000d000

/* system memory from 0x00000000 to 0x0fffffff */
#define	SC520_PCI_MEMORY_PHYS	0x00000000
#define	SC520_PCI_MEMORY_BUS	0x00000000
#define SC520_PCI_MEMORY_SIZE	0x10000000

/* PCI bus memory from 0x10000000 to 0x26ffffff
 * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
#define SC520_PCI_MEM_PHYS	0x10000000
#define SC520_PCI_MEM_BUS	0x10000000
#define SC520_PCI_MEM_SIZE	0x17000000

/* 0x28000000 - 0x3fffffff is used by the flash banks */

/* 0x40000000 - 0xffffffff is not adressable by the SC520 */

/* priority numbers used for interrupt channel mappings */
#define SC520_IRQ_DISABLED 0
#define SC520_IRQ0  1
#define SC520_IRQ1  2
#define SC520_IRQ2  4  /* same as IRQ9 */
#define SC520_IRQ3  11
#define SC520_IRQ4  12
#define SC520_IRQ5  13
#define SC520_IRQ6  21
#define SC520_IRQ7  22
#define SC520_IRQ8  3
#define SC520_IRQ9  4
#define SC520_IRQ10 5
#define SC520_IRQ11 6
#define SC520_IRQ12 7
#define SC520_IRQ13 8
#define SC520_IRQ14 9
#define SC520_IRQ15 10


/* pin number used for PCI interrupt mappings */
#define SC520_PCI_INTA 0
#define SC520_PCI_INTB 1
#define SC520_PCI_INTC 2
#define SC520_PCI_INTD 3
#define SC520_PCI_GPIRQ0 4
#define SC520_PCI_GPIRQ1 5
#define SC520_PCI_GPIRQ2 6
#define SC520_PCI_GPIRQ3 7
#define SC520_PCI_GPIRQ4 8
#define SC520_PCI_GPIRQ5 9
#define SC520_PCI_GPIRQ6 10
#define SC520_PCI_GPIRQ7 11
#define SC520_PCI_GPIRQ8 12
#define SC520_PCI_GPIRQ9 13
#define SC520_PCI_GPIRQ10 14

/* utility functions */
void write_mmcr_byte(u16 mmcr, u8 data);
void write_mmcr_word(u16 mmcr, u16 data);
void write_mmcr_long(u16 mmcr, u32 data);
u8 read_mmcr_byte(u16 mmcr);
u16 read_mmcr_word(u16 mmcr);
u32 read_mmcr_long(u16 mmcr);

extern int sc520_pci_ints[];

void init_sc520(void);
unsigned long init_sc520_dram(void);
void pci_sc520_init(struct pci_controller *hose);
int pci_sc520_set_irq(int pci_pin, int irq);

#endif