linkstation.h

uboot详细解读可用启动引导LINUX2.6内核

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#if 1 /* RAM is available when the first C function is called */
#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000)
#else
#define CFG_INIT_RAM_ADDR	0x40000000
#endif
#define CFG_INIT_RAM_END	0x1000
#define CFG_GBL_DATA_SIZE	128
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*----------------------------------------------------------------------
 * Serial configuration
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		57600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CFG_NS16550
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4600)	/* Console port	*/
#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4500)	/* AVR port	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8245 user's manual.
 *
 * Unless indicated otherwise, the values are
 * taken from the orignal Linkstation boot code
 *
 * Most of the low level configuration setttings are normally used
 * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
 * Low level initialisation is done in board/linkstation/early_init.S
 * The values below are included for reference purpose only
 */

/* FIXME: 32.768 MHz is the crystal frequency but */
/* the real frequency is lower by about 0.75%     */
#define CONFIG_SYS_CLK_FREQ	32768000
#define CFG_HZ			1000

/* Bit-field values for MCCR1.  */
#define CFG_ROMNAL      0
#define CFG_ROMFAL      11

#define CFG_BANK0_ROW	2       /* Only bank 0 used: 13 x n x 4 */
#define CFG_BANK1_ROW	0
#define CFG_BANK2_ROW	0
#define CFG_BANK3_ROW	0
#define CFG_BANK4_ROW	0
#define CFG_BANK5_ROW	0
#define CFG_BANK6_ROW	0
#define CFG_BANK7_ROW	0

/* Bit-field values for MCCR2.  */
#define CFG_TSWAIT      0
#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
#define CFG_REFINT      0x15e0
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
#define CFG_REFINT      0x1580
#endif

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
#define CFG_BSTOPRE	0x91c

/* Bit-field values for MCCR3.  */
#define CFG_REFREC      7

/* Bit-field values for MCCR4.  */
#define CFG_PRETOACT		2
#define CFG_ACTTOPRE		2	/* Original value was 2	*/
#define CFG_ACTORW		2
#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
#define CFG_SDMODE_CAS_LAT	2	/* For 100MHz bus	*/
/*#define CFG_SDMODE_BURSTLEN	3*/
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
#define CFG_SDMODE_CAS_LAT	3	/* For 133MHz bus	*/
/*#define CFG_SDMODE_BURSTLEN	2*/
#endif
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM		1	/* Original setting but there is no EXTROM */
#define CFG_REGDIMM		0
#define CFG_DBUS_SIZE2		1
#define CFG_SDMODE_WRAP		0

#define CFG_PGMAX		0x32	/* All boards use this setting. Original 0x92 */
#define CFG_SDRAM_DSCD		0x30

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CFG_BANK0_START	    0x00000000
#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE    1
#define CFG_BANK1_START     0x3ff00000
#define CFG_BANK1_END       0x3fffffff
#define CFG_BANK1_ENABLE    0
#define CFG_BANK2_START     0x3ff00000
#define CFG_BANK2_END       0x3fffffff
#define CFG_BANK2_ENABLE    0
#define CFG_BANK3_START     0x3ff00000
#define CFG_BANK3_END       0x3fffffff
#define CFG_BANK3_ENABLE    0
#define CFG_BANK4_START     0x3ff00000
#define CFG_BANK4_END       0x3fffffff
#define CFG_BANK4_ENABLE    0
#define CFG_BANK5_START     0x3ff00000
#define CFG_BANK5_END       0x3fffffff
#define CFG_BANK5_ENABLE    0
#define CFG_BANK6_START     0x3ff00000
#define CFG_BANK6_END       0x3fffffff
#define CFG_BANK6_ENABLE    0
#define CFG_BANK7_START     0x3ff00000
#define CFG_BANK7_END       0x3fffffff
#define CFG_BANK7_ENABLE    0

#define CFG_ODCR	    0x15

/*----------------------------------------------------------------------
 * Initial BAT mappings
 */

/* NOTES:
 * 1) GUARDED and WRITETHROUGH not allowed in IBATS
 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 */

/* SDRAM */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)

#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

/* EUMB: 1MB of address space */
#define CFG_IBAT1L	(CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT1U	(CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)

#define CFG_DBAT1L	(CFG_IBAT1L | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U	CFG_IBAT1U

/* PCI Mem: 256MB of address space */
#define CFG_IBAT2L	(CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U	(CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT2L	(CFG_IBAT2L | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U	CFG_IBAT2U

/* PCI and local ROM/Flash: last 32MB of address space */
#define CFG_IBAT3L	(CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U	(CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)

#define CFG_DBAT3L	(CFG_IBAT3L | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U	CFG_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 *
 * FIXME: This doesn't appear to be true for the newer kernels
 * which map more that 8 MB
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#undef  CFG_FLASH_PROTECTION
#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	72	/* Max number of sectors per flash	*/

#define CFG_FLASH_ERASE_TOUT	12000
#define CFG_FLASH_WRITE_TOUT	1000

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CFG_ENV_IS_IN_FLASH
/*
 * The original LinkStation flash organisation uses
 * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader
 * We use the last sector of this area to store the environment
 * which leaves max. 384 kB for the U-Boot itself
 */
#define CFG_ENV_ADDR		0xFFF60000
#define CFG_ENV_SIZE		0x00010000
#define CFG_ENV_SECT_SIZE	0x00010000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * IDE/ATA definitions
 */
#undef  CONFIG_IDE_LED				/* No IDE LED			*/
#define CONFIG_IDE_RESET			/* no reset for ide supported	*/
#define CONFIG_IDE_PREINIT			/* check for units		*/
#define CONFIG_LBA48				/* 48 bit LBA supported		*/

#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN)
#define CFG_IDE_MAXBUS		1		/* Scan only 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1		/* Only 1 drive per IDE bus	*/
#elif defined(CONFIG_HGTL)
#define CFG_IDE_MAXBUS		2		/* Max. 2 IDE busses		*/
#define CFG_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
#else
#error Config IDE: Unknown LinkStation type
#endif

#define CFG_ATA_BASE_ADDR	0

#define CFG_ATA_DATA_OFFSET	0		/* Offset for data I/O		*/
#define CFG_ATA_REG_OFFSET	0		/* Offset for normal registers	*/
#define CFG_ATA_ALT_OFFSET	0		/* Offset for alternate registers */

/*-----------------------------------------------------------------------
 * Partitions and file system
 */
#define CONFIG_DOS_PARTITION

/*-----------------------------------------------------------------------
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#endif	/* __CONFIG_H */