sc3.h

uboot详细解读可用启动引导LINUX2.6内核

#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#else
#define CONFIG_START_IDE	1	/* check, if use IDE */

#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/

#define	CONFIG_ATAPI
#define	CONFIG_DOS_PARTITION
#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#ifndef IDE_USES_ISA_EMULATION

/* New and faster access */
#define	CFG_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */

/* How many IDE busses are available */
#define	CFG_IDE_MAXBUS		1

/* What IDE ports are available */
#define	CFG_ATA_IDE0_OFFSET	0x000		/* first is available */
#undef	CFG_ATA_IDE1_OFFSET			/* second not available */

/* access to the data port is calculated:
   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */

/* access to the registers is calculated:
   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/

/* access to the alternate register is calculated:
   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
#define CFG_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/

#else /* IDE_USES_ISA_EMULATION */

#define	CFG_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */

/* How many IDE busses are available */
#define	CFG_IDE_MAXBUS		1

/* What IDE ports are available */
#define	CFG_ATA_IDE0_OFFSET	0x01F0	/* first is available */
#undef	CFG_ATA_IDE1_OFFSET				/* second not available */

/* access to the data port is calculated:
   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */

/* access to the registers is calculated:
   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/

/* access to the alternate register is calculated:
   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
#define CFG_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/

#endif /* IDE_USES_ISA_EMULATION */

#endif

/*
#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
#define	CFG_IR_REG_BASE_ADDR	0xF0200000
#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 *
 * CFG_FLASH_BASE   -> start address of internal flash
 * CFG_MONITOR_BASE -> start of u-boot
 */
#ifndef __ASSEMBLER__
extern unsigned long offsetOfBigFlash;
extern unsigned long offsetOfEnvironment;
#endif

#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFE00000
#define CFG_MONITOR_BASE	0xFFFC0000     /* placed last 256k */
#define CFG_MONITOR_LEN		(224 * 1024)	/* Reserve 224 KiB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MiB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization ## FIXME: lookup in datasheet
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_CFI			/* flash is CFI compat.	*/
#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
#define CFG_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */

#define CFG_ENV_IS_IN_FLASH	1
#if CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET		0x00000000  /* Offset of Environment Sector in bottom type */
#define CFG_ENV_SIZE		0x4000	    /* Total Size of Environment Sector	*/
#define CFG_ENV_SECT_SIZE	0x4000	    /* see README - env sector total size	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

#endif
/* let us changing anything in our environment */
#define CONFIG_ENV_OVERWRITE

/*
 * NAND-FLASH stuff
 */
#define CFG_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1
#define CFG_NAND_BASE		0x77D00000


#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */

/* No command line, one static partition */
#undef	CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nand0"
#define CONFIG_JFFS2_PART_SIZE		0x01000000
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/*
 * Init Memory Controller:
 *
 */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
#define FLASH_BASE1_PRELIM	0

/*-----------------------------------------------------------------------
 * Some informations about the internal SRAM (OCM=On Chip Memory)
 *
 * CFG_OCM_DATA_ADDR -> location
 * CFG_OCM_DATA_SIZE -> size
*/

#define CFG_TEMP_STACK_OCM	1
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM):
 * - we are using the internal 4k SRAM, so we don't need data cache mapping
 * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
 * - Stackpointer will be located to
 *   (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
 *   in cpu/ppc4xx/start.S
 */

#undef CFG_INIT_DCACHE_CS
/* Where the internal SRAM starts */
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
/* Where the internal SRAM ends (only offset) */
#define CFG_INIT_RAM_END	0x0F00

/*

 CFG_INIT_RAM_ADDR ------> ------------ lower address
			   |	      |
			   |  ^       |
			   |  |       |
			   |  | Stack |
 CFG_GBL_DATA_OFFSET ----> ------------
			   |	      |
			   | 64 Bytes |
			   |	      |
 CFG_INIT_RAM_END  ------> ------------ higher address
  (offset only)

*/
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE     64
#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* Initial value of the stack pointern in internal SRAM */
#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/* ################################################################################### */
/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects  */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S   */

/* This chip select accesses the boot device */
/* It depends on boot select switch if this device is 16 or 8 bit */

#undef CFG_EBC_PB0AP
#undef CFG_EBC_PB0CR

#undef CFG_EBC_PB1AP
#undef CFG_EBC_PB1CR

#undef CFG_EBC_PB2AP
#undef CFG_EBC_PB2CR

#undef CFG_EBC_PB3AP
#undef CFG_EBC_PB3CR

#undef CFG_EBC_PB4AP
#undef CFG_EBC_PB4CR

#undef CFG_EBC_PB5AP
#undef CFG_EBC_PB5CR

#undef CFG_EBC_PB6AP
#undef CFG_EBC_PB6CR

#undef CFG_EBC_PB7AP
#undef CFG_EBC_PB7CR

#define CFG_EBC_CFG    0xb84ef000

#define CONFIG_SDRAM_BANK0	/* use the standard SDRAM initialization */
#undef CONFIG_SPD_EEPROM

/*
 * Define this to get more information about system configuration
 */
/* #define SC3_DEBUGOUT */
#undef SC3_DEBUGOUT

/***********************************************************************
 * External peripheral base address
 ***********************************************************************/

#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
/*
 Die Grafik-Treiber greifen 黚er die Adresse in diesem Macro auf den Chip zu.
 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
 das gleiche Mapping durchf黨ren kann, wie der SC520 (also Aufteilen von IO-Zugriffen
 auf ISA- und PCI-Zyklen)
 */
#define CFG_ISA_IO_BASE_ADDRESS  0xE8000000
/*#define CFG_ISA_IO_BASE_ADDRESS  0x79000000 */

/************************************************************
 * Video support
 ************************************************************/

#ifdef USE_VGA_GRAPHICS
#define CONFIG_VIDEO		/* To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
/* #define CONFIG_VIDEO_LOGO */
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
/* #define CONFIG_VIDEO_HW_CURSOR */
#define CONFIG_VIDEO_ONBOARD	/* Video controller is on-board */

#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT

#endif

/************************************************************
 * Ident
 ************************************************************/
#define CONFIG_SC3_VERSION "r1.4"

#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)

#endif	/* __CONFIG_H */