apc405.h

uboot详细解读可用启动引导LINUX2.6内核

#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef  CONFIG_IDE_LED			/* no led for ide supported */
#define CONFIG_IDE_RESET	1	/* reset for ide supported */

#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_MONITOR_BASE	0xFFF80000
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor */
#define CFG_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Init. Memory map for Linux */

/*
 * FLASH organization
 */
#ifndef __ASSEMBLY__
extern int flash_banks;
#endif

#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
#define CFG_MAX_FLASH_BANKS	flash_banks /* max num of flash banks */
					    /* updated in board_early_init_r */
#define CFG_MAX_FLASH_BANKS_DETECT 2
#define CFG_FLASH_QUIET_TEST	1
#define CFG_FLASH_INCREMENT	0x01000000
#define CFG_FLASH_PROTECTION	1	/* use hardware protection */
#define CFG_FLASH_AUTOPROTECT_LIST { \
				{0xfe000000, 0x500000}, \
				{0xffe80000, 0x180000} \
				}
#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
#define CFG_FLASH_BANKS_LIST	{ \
				CFG_FLASH_BASE, \
				CFG_FLASH_BASE + CFG_FLASH_INCREMENT \
				}
#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */

/*
 * Environment Variable setup
 */
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x000	/* environment starts at the */
					/* beginning of the EEPROM */
#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting vendor vars */

#define CFG_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
#define CFG_NVRAM_SIZE		242		/* NVRAM size */

/*
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08 */
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
					/* 16 byte page write mode using*/
					/* last	4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*
 * External Bus Controller (EBC) Setup
 */
#define FLASH0_BA       (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */
#define FLASH1_BA       CFG_FLASH_BASE      /* FLASH 1 Base Address          */
#define CAN_BA          0xF0000000          /* CAN Base Address              */
#define DUART0_BA       0xF0000400          /* DUART Base Address            */
#define DUART1_BA       0xF0000408          /* DUART Base Address            */
#define RTC_BA          0xF0000500          /* RTC Base Address              */
#define PS2_BA          0xF0000600          /* PS/2 Base Address             */
#define CF_BA           0xF0100000          /* CompactFlash Base Address     */
#define FPGA_BA         0xF0100100          /* FPGA internal Base Address    */
#define FUJI_BA         0xF0100200          /* Fuji internal Base Address    */
#define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address    */
#define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address    */
#define VGA_BA          0xF1000000          /* Epson VGA Base Address        */

#define CFG_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */

/* Memory Bank 0 (Flash Bank 0) initialization                               */
#define CFG_EBC_PB0AP   0x92015480
#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
#define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP
#define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */

/* Memory Bank 1 (Flash Bank 1) initialization                               */
#define CFG_EBC_PB1AP   0x92015480
#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/

/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
#define CFG_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/

/* Memory Bank 5 (Epson VGA) initialization                                     */
#define CFG_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
#define CFG_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
#define CFG_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/

/*
 * FPGA stuff
 */

/* FPGA internal regs */
#define CFG_FPGA_CTRL           0x008
#define CFG_FPGA_CTRL2          0x00a

/* FPGA Control Reg */
#define CFG_FPGA_CTRL_CF_RESET  0x0001
#define CFG_FPGA_CTRL_WDI       0x0002
#define CFG_FPGA_CTRL_PS2_RESET 0x0020

#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */

/*
 * LCD Setup
 */
#define CFG_LCD_BIG_MEM		(VGA_BA + 0x200000) /* S1D13806 Mem Base */
#define CFG_LCD_BIG_REG		VGA_BA /* S1D13806 Reg Base */

#define CONFIG_LCD_BIG		2 /* Epson S1D13806 used */

/* Image information... */
#define CONFIG_LCD_USED		CONFIG_LCD_BIG

#define CFG_LCD_MEM		CFG_LCD_BIG_MEM
#define CFG_LCD_REG		CFG_LCD_BIG_REG

#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)

/*
 * Definitions for initial stack pointer and data area (in data cache)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000

#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM */
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE	128 /* reserved bytes for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* reserve some memory for BOOT limit info */
#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 16)

#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 8)
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

/*
 * PCI OHCI controller
 */
#define CONFIG_USB_OHCI_NEW	1
#define CONFIG_PCI_OHCI		1
#define CFG_OHCI_SWAP_REG_ACCESS 1
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CFG_USB_OHCI_SLOT_NAME	"ohci_pci"
#define CONFIG_USB_STORAGE	1
#define CFG_USB_OHCI_BOARD_INIT 1

#endif /* __CONFIG_H */