ati_radeon_fb.c

uboot详细解读可用启动引导LINUX2.6内核

	switch (bpp) {
	case 24:
		mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
#if defined(__BIG_ENDIAN)
		mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
		mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
#endif
		break;
	case 16:
		mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
#if defined(__BIG_ENDIAN)
		mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
		mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
#endif
		break;
	default:
		mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
		mode->surface_cntl = 0x00000000;
		break;
	}

	switch (vesa_idx) {
	case RES_MODE_1280x1024:
		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
		mode->ppll_div_3 = 0x00010078;
#else /* default @ 60 Hz */
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
		mode->ppll_div_3 = 0x00010060;
#endif
		/*
		 * for this mode pitch expands to the same value for 32, 16 and 8 bpp,
		 * so we set it here once only.
		 */
		mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
		switch (bpp) {
		case 24:
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
			break;
		case 16:
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
			break;
		default: /* 8 bpp */
			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
			break;
		}
		break;
	case RES_MODE_1024x768:
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
		mode->ppll_div_3 = 0x0002008c;
#else /* @ 60 Hz */
		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
		mode->ppll_div_3 = 0x00020074;
#endif
		/* also same pitch value for 32, 16 and 8 bpp */
		mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
		switch (bpp) {
		case 24:
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
			break;
		case 16:
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
			break;
		default: /* 8 bpp */
			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
			break;
		}
		break;
	case RES_MODE_800x600:
		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
		mode->ppll_div_3 = 0x000300b0;
#else /* @ 60 Hz */
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
		mode->ppll_div_3 = 0x0003008e;
#endif
		switch (bpp) {
		case 24:
			mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
			break;
		case 16:
			mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
			break;
		default: /* 8 bpp */
			mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
			break;
		}
		break;
	default: /* RES_MODE_640x480 */
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
		mode->ppll_div_3 = 0x00030070;
#else /* @ 60 Hz */
		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
		mode->ppll_div_3 = 0x00030059;
#endif
		/* also same pitch value for 32, 16 and 8 bpp */
		mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
		switch (bpp) {
		case 24:
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
			break;
		case 16:
			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
			break;
		default: /* 8 bpp */
			mode->crtc_offset_cntl = 0x00000000;
			break;
		}
		break;
	}

	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
		(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
	OUTREG(CRTC_OFFSET, 0);
	OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
	OUTREG(CRTC_PITCH, mode->crtc_pitch);
	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);

	mode->clk_cntl_index = 0x300;
	mode->ppll_ref_div = 0xc;

	radeon_write_pll_regs(rinfo, mode);

	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
		~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
	OUTREG(SURFACE0_INFO, mode->surf_info[0]);
	OUTREG(SURFACE0_LOWER_BOUND, 0);
	OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
	OUTREG(SURFACE_CNTL, mode->surface_cntl);

	if (bpp > 8)
		set_pal();

	free(mode);
}

#include "../bios_emulator/include/biosemu.h"
extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);

int radeon_probe(struct radeonfb_info *rinfo)
{
	pci_dev_t pdev;
	u16 did;

	pdev = pci_find_devices(ati_radeon_pci_ids, 0);

	if (pdev != -1) {
		pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
		printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
				PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
				(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);

		strcpy(rinfo->name, "ATI Radeon");
		rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
		rinfo->pdev.device = did;
		rinfo->family = get_radeon_id_family(rinfo->pdev.device);
		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
				&rinfo->fb_base_phys);
		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
				&rinfo->mmio_base_phys);
		rinfo->fb_base_phys &= 0xfffff000;
		rinfo->mmio_base_phys &= ~0x04;

		rinfo->mmio_base = (void *)rinfo->mmio_base_phys;
		DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base);
		rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
		DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
		/* PostBIOS with x86 emulater */
		BootVideoCardBIOS(pdev, NULL, 0);

		/*
		 * Check for errata
		 * (These will be added in the future for the chipfamily
		 * R300, RV200, RS200, RV100, RS100.)
		 */

		/* Get VRAM size and type */
		radeon_identify_vram(rinfo);

		rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
				rinfo->video_ram);
		rinfo->fb_base = (void *)rinfo->fb_base_phys;

		DPRINT("Radeon: framebuffer base phy address 0x%08x," \
		      "MMIO base phy address 0x%08x," \
		      "framebuffer local base 0x%08x.\n ",
		      rinfo->fb_base_phys, rinfo->mmio_base_phys,
		      rinfo->fb_local_base);

		return 0;
	}
	return -1;
}

/*
 * The Graphic Device
 */
GraphicDevice ctfb;

#define CURSOR_SIZE	0x1000	/* in KByte for HW Cursor */
#define PATTERN_ADR	(pGD->dprBase + CURSOR_SIZE)	/* pattern Memory after Cursor Memory */
#define PATTERN_SIZE	8*8*4	/* 4 Bytes per Pixel 8 x 8 Pixel */
#define ACCELMEMORY	(CURSOR_SIZE + PATTERN_SIZE)	/* reserved Memory for BITBlt and hw cursor */

void *video_hw_init(void)
{
	GraphicDevice *pGD = (GraphicDevice *) & ctfb;
	u32 *vm;
	char *penv;
	unsigned long t1, hsynch, vsynch;
	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
	struct ctfb_res_modes *res_mode;
	struct ctfb_res_modes var_mode;

	rinfo = malloc(sizeof(struct radeonfb_info));

	printf("Video: ");
	if(radeon_probe(rinfo)) {
		printf("No radeon video card found!\n");
		return NULL;
	}

	tmp = 0;

	videomode = CFG_DEFAULT_VIDEO_MODE;
	/* get video mode via environment */
	if ((penv = getenv ("videomode")) != NULL) {
		/* deceide if it is a string */
		if (penv[0] <= '9') {
			videomode = (int) simple_strtoul (penv, NULL, 16);
			tmp = 1;
		}
	} else {
		tmp = 1;
	}
	if (tmp) {
		/* parameter are vesa modes */
		/* search params */
		for (i = 0; i < VESA_MODES_COUNT; i++) {
			if (vesa_modes[i].vesanr == videomode)
				break;
		}
		if (i == VESA_MODES_COUNT) {
			printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE);
			i = 0;
		}
		res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
		bits_per_pixel = vesa_modes[i].bits_per_pixel;
		vesa_idx = vesa_modes[i].resindex;
	} else {
		res_mode = (struct ctfb_res_modes *) &var_mode;
		bits_per_pixel = video_get_params (res_mode, penv);
	}

	/* calculate hsynch and vsynch freq (info only) */
	t1 = (res_mode->left_margin + res_mode->xres +
	      res_mode->right_margin + res_mode->hsync_len) / 8;
	t1 *= 8;
	t1 *= res_mode->pixclock;
	t1 /= 1000;
	hsynch = 1000000000L / t1;
	t1 *= (res_mode->upper_margin + res_mode->yres +
	       res_mode->lower_margin + res_mode->vsync_len);
	t1 /= 1000;
	vsynch = 1000000000L / t1;

	/* fill in Graphic device struct */
	sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
		 res_mode->yres, bits_per_pixel, (hsynch / 1000),
		 (vsynch / 1000));
	printf ("%s\n", pGD->modeIdent);
	pGD->winSizeX = res_mode->xres;
	pGD->winSizeY = res_mode->yres;
	pGD->plnSizeX = res_mode->xres;
	pGD->plnSizeY = res_mode->yres;

	switch (bits_per_pixel) {
	case 24:
		pGD->gdfBytesPP = 4;
		pGD->gdfIndex = GDF_32BIT_X888RGB;
		if (res_mode->xres == 800) {
			pGD->winSizeX = 832;
			pGD->plnSizeX = 832;
		}
		break;
	case 16:
		pGD->gdfBytesPP = 2;
		pGD->gdfIndex = GDF_16BIT_565RGB;
		if (res_mode->xres == 800) {
			pGD->winSizeX = 896;
			pGD->plnSizeX = 896;
		}
		break;
	default:
		if (res_mode->xres == 800) {
			pGD->winSizeX = 1024;
			pGD->plnSizeX = 1024;
		}
		pGD->gdfBytesPP = 1;
		pGD->gdfIndex = GDF__8BIT_INDEX;
		break;
	}

	pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
	pGD->pciBase = rinfo->fb_base_phys;
	pGD->frameAdrs = rinfo->fb_base_phys;
	pGD->memSize = 64 * 1024 * 1024;

	/* Cursor Start Address */
	pGD->dprBase =
	    (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys;
	if ((pGD->dprBase & 0x0fff) != 0) {
		/* allign it */
		pGD->dprBase &= 0xfffff000;
		pGD->dprBase += 0x00001000;
	}
	DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
		PATTERN_ADR);
	pGD->vprBase = rinfo->fb_base_phys;	/* Dummy */
	pGD->cprBase = rinfo->fb_base_phys;	/* Dummy */
	/* set up Hardware */

	/* Clear video memory (only visible screen area) */
	i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
	vm = (unsigned int *) pGD->pciBase;
	while (i--)
		*vm++ = 0;
	/*SetDrawingEngine (bits_per_pixel);*/

	if (rinfo->family == CHIP_FAMILY_RV280)
		radeon_setmode_9200(vesa_idx, bits_per_pixel);
	else
		radeon_setmode();

	return ((void *) pGD);
}

void video_set_lut (unsigned int index,	/* color number */
	       unsigned char r,	/* red */
	       unsigned char g,	/* green */
	       unsigned char b	/* blue */
	       )
{
	OUTREG(PALETTE_INDEX, index);
	OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b);
}
#endif