e1000.h

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#define EEPROM_ERASE_OPCODE 0x7	/* EERPOM erase opcode */
#define EEPROM_EWEN_OPCODE  0x13	/* EERPOM erase/write enable */
#define EEPROM_EWDS_OPCODE  0x10	/* EERPOM erast/write disable */

/* EEPROM Word Offsets */
#define EEPROM_COMPAT		   0x0003
#define EEPROM_ID_LED_SETTINGS	   0x0004
#define EEPROM_INIT_CONTROL1_REG   0x000A
#define EEPROM_INIT_CONTROL2_REG   0x000F
#define EEPROM_FLASH_VERSION	   0x0032
#define EEPROM_CHECKSUM_REG	   0x003F

/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000
#define ID_LED_RESERVED_FFFF 0xFFFF
#define ID_LED_DEFAULT	     ((ID_LED_OFF1_ON2 << 12) | \
			      (ID_LED_OFF1_OFF2 << 8) | \
			      (ID_LED_DEF1_DEF2 << 4) | \
			      (ID_LED_DEF1_DEF2))
#define ID_LED_DEF1_DEF2     0x1
#define ID_LED_DEF1_ON2      0x2
#define ID_LED_DEF1_OFF2     0x3
#define ID_LED_ON1_DEF2      0x4
#define ID_LED_ON1_ON2	     0x5
#define ID_LED_ON1_OFF2      0x6
#define ID_LED_OFF1_DEF2     0x7
#define ID_LED_OFF1_ON2      0x8
#define ID_LED_OFF1_OFF2     0x9

/* Mask bits for fields in Word 0x03 of the EEPROM */
#define EEPROM_COMPAT_SERVER 0x0400
#define EEPROM_COMPAT_CLIENT 0x0200

/* Mask bits for fields in Word 0x0a of the EEPROM */
#define EEPROM_WORD0A_ILOS   0x0010
#define EEPROM_WORD0A_SWDPIO 0x01E0
#define EEPROM_WORD0A_LRST   0x0200
#define EEPROM_WORD0A_FD     0x0400
#define EEPROM_WORD0A_66MHZ  0x0800

/* Mask bits for fields in Word 0x0f of the EEPROM */
#define EEPROM_WORD0F_PAUSE_MASK 0x3000
#define EEPROM_WORD0F_PAUSE	 0x1000
#define EEPROM_WORD0F_ASM_DIR	 0x2000
#define EEPROM_WORD0F_ANE	 0x0800
#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0

/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
#define EEPROM_SUM 0xBABA

/* EEPROM Map defines (WORD OFFSETS)*/
#define EEPROM_NODE_ADDRESS_BYTE_0 0
#define EEPROM_PBA_BYTE_1	   8

/* EEPROM Map Sizes (Byte Counts) */
#define PBA_SIZE 4

/* Collision related configuration parameters */
#define E1000_COLLISION_THRESHOLD	16
#define E1000_CT_SHIFT			4
#define E1000_COLLISION_DISTANCE	64
#define E1000_FDX_COLLISION_DISTANCE	E1000_COLLISION_DISTANCE
#define E1000_HDX_COLLISION_DISTANCE	E1000_COLLISION_DISTANCE
#define E1000_GB_HDX_COLLISION_DISTANCE 512
#define E1000_COLD_SHIFT		12

/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
#define REQ_TX_DESCRIPTOR_MULTIPLE  8
#define REQ_RX_DESCRIPTOR_MULTIPLE  8

/* Default values for the transmit IPG register */
#define DEFAULT_82542_TIPG_IPGT        10
#define DEFAULT_82543_TIPG_IPGT_FIBER  9
#define DEFAULT_82543_TIPG_IPGT_COPPER 8

#define E1000_TIPG_IPGT_MASK  0x000003FF
#define E1000_TIPG_IPGR1_MASK 0x000FFC00
#define E1000_TIPG_IPGR2_MASK 0x3FF00000

#define DEFAULT_82542_TIPG_IPGR1 2
#define DEFAULT_82543_TIPG_IPGR1 8
#define E1000_TIPG_IPGR1_SHIFT	10

#define DEFAULT_82542_TIPG_IPGR2 10
#define DEFAULT_82543_TIPG_IPGR2 6
#define E1000_TIPG_IPGR2_SHIFT	20

#define E1000_TXDMAC_DPP 0x00000001

/* Adaptive IFS defines */
#define TX_THRESHOLD_START     8
#define TX_THRESHOLD_INCREMENT 10
#define TX_THRESHOLD_DECREMENT 1
#define TX_THRESHOLD_STOP      190
#define TX_THRESHOLD_DISABLE   0
#define TX_THRESHOLD_TIMER_MS  10000
#define MIN_NUM_XMITS	       1000
#define IFS_MAX		       80
#define IFS_STEP	       10
#define IFS_MIN		       40
#define IFS_RATIO	       4

/* PBA constants */
#define E1000_PBA_16K 0x0010	/* 16KB, default TX allocation */
#define E1000_PBA_24K 0x0018
#define E1000_PBA_40K 0x0028
#define E1000_PBA_48K 0x0030	/* 48KB, default RX allocation */

/* Flow Control Constants */
#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
#define FLOW_CONTROL_TYPE	  0x8808

/* The historical defaults for the flow control values are given below. */
#define FC_DEFAULT_HI_THRESH	    (0x8000)	/* 32KB */
#define FC_DEFAULT_LO_THRESH	    (0x4000)	/* 16KB */
#define FC_DEFAULT_TX_TIMER	    (0x100)	/* ~130 us */

/* Flow Control High-Watermark: 43464 bytes */
#define E1000_FC_HIGH_THRESH 0xA9C8
/* Flow Control Low-Watermark: 43456 bytes */
#define E1000_FC_LOW_THRESH 0xA9C0
/* Flow Control Pause Time: 858 usec */
#define E1000_FC_PAUSE_TIME 0x0680

/* PCIX Config space */
#define PCIX_COMMAND_REGISTER	 0xE6
#define PCIX_STATUS_REGISTER_LO  0xE8
#define PCIX_STATUS_REGISTER_HI  0xEA

#define PCIX_COMMAND_MMRBC_MASK      0x000C
#define PCIX_COMMAND_MMRBC_SHIFT     0x2
#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
#define PCIX_STATUS_HI_MMRBC_4K      0x3
#define PCIX_STATUS_HI_MMRBC_2K      0x2

/* The number of bits that we need to shift right to move the "pause"
 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
 * in the TXCW register
 */
#define PAUSE_SHIFT 5

/* The number of bits that we need to shift left to move the "SWDPIO"
 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
 * in the CTRL register
 */
#define SWDPIO_SHIFT 17

/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
 * Extended CTRL register.
 * in the CTRL register
 */
#define SWDPIO__EXT_SHIFT 4

/* The number of bits that we need to shift left to move the "ILOS"
 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
 * in the CTRL register
 */
#define ILOS_SHIFT  3

#define RECEIVE_BUFFER_ALIGN_SIZE  (256)

/* The number of milliseconds we wait for auto-negotiation to complete */
#define LINK_UP_TIMEOUT		    500

#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)

/* The carrier extension symbol, as received by the NIC. */
#define CARRIER_EXTENSION   0x0F

/* TBI_ACCEPT macro definition:
 *
 * This macro requires:
 *	adapter = a pointer to struct e1000_hw
 *	status = the 8 bit status field of the RX descriptor with EOP set
 *	error = the 8 bit error field of the RX descriptor with EOP set
 *	length = the sum of all the length fields of the RX descriptors that
 *		 make up the current frame
 *	last_byte = the last byte of the frame DMAed by the hardware
 *	max_frame_length = the maximum frame length we want to accept.
 *	min_frame_length = the minimum frame length we want to accept.
 *
 * This macro is a conditional that should be used in the interrupt
 * handler's Rx processing routine when RxErrors have been detected.
 *
 * Typical use:
 *  ...
 *  if (TBI_ACCEPT) {
 *	accept_frame = TRUE;
 *	e1000_tbi_adjust_stats(adapter, MacAddress);
 *	frame_length--;
 *  } else {
 *	accept_frame = FALSE;
 *  }
 *  ...
 */

#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
    ((adapter)->tbi_compatibility_on && \
     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
     ((last_byte) == CARRIER_EXTENSION) && \
     (((status) & E1000_RXD_STAT_VP) ? \
	  (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
	   ((length) <= ((adapter)->max_frame_size + 1))) : \
	  (((length) > (adapter)->min_frame_size) && \
	   ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))

/* Structures, enums, and macros for the PHY */

/* Bit definitions for the Management Data IO (MDIO) and Management Data
 * Clock (MDC) pins in the Device Control Register.
 */
#define E1000_CTRL_PHY_RESET_DIR	E1000_CTRL_SWDPIO0
#define E1000_CTRL_PHY_RESET		E1000_CTRL_SWDPIN0
#define E1000_CTRL_MDIO_DIR		E1000_CTRL_SWDPIO2
#define E1000_CTRL_MDIO			E1000_CTRL_SWDPIN2
#define E1000_CTRL_MDC_DIR		E1000_CTRL_SWDPIO3
#define E1000_CTRL_MDC			E1000_CTRL_SWDPIN3
#define E1000_CTRL_PHY_RESET_DIR4	E1000_CTRL_EXT_SDP4_DIR
#define E1000_CTRL_PHY_RESET4		E1000_CTRL_EXT_SDP4_DATA

/* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */
#define PHY_CTRL			0x00	/* Control Register */
#define PHY_STATUS			0x01	/* Status Regiser */
#define PHY_ID1				0x02	/* Phy Id Reg (word 1) */
#define PHY_ID2				0x03	/* Phy Id Reg (word 2) */
#define PHY_AUTONEG_ADV		0x04	/* Autoneg Advertisement */
#define PHY_LP_ABILITY			0x05	/* Link Partner Ability (Base Page) */
#define PHY_AUTONEG_EXP		0x06	/* Autoneg Expansion Reg */
#define PHY_NEXT_PAGE_TX		0x07	/* Next Page TX */
#define PHY_LP_NEXT_PAGE		0x08	/* Link Partner Next Page */
#define PHY_1000T_CTRL			0x09	/* 1000Base-T Control Reg */
#define PHY_1000T_STATUS		0x0A	/* 1000Base-T Status Reg */
#define PHY_EXT_STATUS			0x0F	/* Extended Status Reg */

/* M88E1000 Specific Registers */
#define M88E1000_PHY_SPEC_CTRL		0x10	/* PHY Specific Control Register */
#define M88E1000_PHY_SPEC_STATUS	0x11	/* PHY Specific Status Register */
#define M88E1000_INT_ENABLE		0x12	/* Interrupt Enable Register */
#define M88E1000_INT_STATUS		0x13	/* Interrupt Status Register */
#define M88E1000_EXT_PHY_SPEC_CTRL	0x14	/* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR		0x15	/* Receive Error Counter */

#define MAX_PHY_REG_ADDRESS		0x1F	/* 5 bit address bus (0-0x1F) */

/* IGP01E1000 specifics */
#define IGP01E1000_IEEE_REGS_PAGE	0x0000
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
#define IGP01E1000_IEEE_FORCE_GIGA	0x0140

/* IGP01E1000 Specific Registers */
#define IGP01E1000_PHY_PORT_CONFIG	0x10 /* PHY Specific Port Config Register */
#define IGP01E1000_PHY_PORT_STATUS	0x11 /* PHY Specific Status Register */
#define IGP01E1000_PHY_PORT_CTRL	0x12 /* PHY Specific Control Register */
#define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health Register */
#define IGP01E1000_GMII_FIFO		0x14 /* GMII FIFO Register */
#define IGP01E1000_PHY_CHANNEL_QUALITY	0x15 /* PHY Channel Quality Register */
#define IGP02E1000_PHY_POWER_MGMT	0x19
#define IGP01E1000_PHY_PAGE_SELECT	0x1F /* PHY Page Select Core Register */

/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB		0x0040	/* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE		0x0080	/* Collision test enable */
#define MII_CR_FULL_DUPLEX		0x0100	/* FDX =1, half duplex =0 */
#define MII_CR_RESTART_AUTO_NEG		0x0200	/* Restart auto negotiation */
#define MII_CR_ISOLATE			0x0400	/* Isolate PHY from MII */
#define MII_CR_POWER_DOWN		0x0800	/* Power down */
#define MII_CR_AUTO_NEG_EN		0x1000	/* Auto Neg Enable */
#define MII_CR_SPEED_SELECT_LSB		0x2000	/* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_LOOPBACK			0x4000	/* 0 = normal, 1 = loopback */
#define MII_CR_RESET			0x8000	/* 0 = normal, 1 = PHY reset */

/* PHY Status Register */
#define MII_SR_EXTENDED_CAPS		0x0001	/* Extended register capabilities */
#define MII_SR_JABBER_DETECT		0x0002	/* Jabber Detected */
#define MII_SR_LINK_STATUS		0x0004	/* Link Status 1 = link */
#define MII_SR_AUTONEG_CAPS		0x0008	/* Auto Neg Capable */
#define MII_SR_REMOTE_FAULT		0x0010	/* Remote Fault Detect */
#define MII_SR_AUTONEG_COMPLETE		0x0020	/* Auto Neg Complete */
#define MII_SR_PREAMBLE_SUPPRESS	0x0040	/* Preamble may be suppressed */
#define MII_SR_EXTENDED_STATUS		0x0100	/* Ext. status info in Reg 0x0F */
#define MII_SR_100T2_HD_CAPS		0x0200	/* 100T2 Half Duplex Capable */
#define MII_SR_100T2_FD_CAPS		0x0400	/* 100T2 Full Duplex Capable */
#define MII_SR_10T_HD_CAPS		0x0800	/* 10T	 Half Duplex Capable */
#define MII_SR_10T_FD_CAPS		0x1000	/* 10T	 Full Duplex Capable */
#define MII_SR_100X_HD_CAPS		0x2000	/* 100X  Half Duplex Capable */
#define MII_SR_100X_FD_CAPS		0x4000	/* 100X  Full Duplex Capable */
#define MII_SR_100T4_CAPS		0x8000	/* 100T4 Capable */

/* Autoneg Advertisement Register */
#define NWAY_AR_SELECTOR_FIELD		0x0001	/* indicates IEEE 802.3 CSMA/CD */
#define NWAY_AR_10T_HD_CAPS		0x0020	/* 10T	 Half Duplex Capable */
#define NWAY_AR_10T_FD_CAPS		0x0040	/* 10T	 Full Duplex Capable */
#define NWAY_AR_100TX_HD_CAPS		0x0080	/* 100TX Half Duplex Capable */
#define NWAY_AR_100TX_FD_CAPS		0x0100	/* 100TX Full Duplex Capable */
#define NWAY_AR_100T4_CAPS		0x0200	/* 100T4 Capable */
#define NWAY_AR_PAUSE			0x0400	/* Pause operation desired */
#define NWAY_AR_ASM_DIR		0x0800	/* Asymmetric Pause Direction bit */
#define NWAY_AR_REMOTE_FAULT		0x2000	/* Remote Fault detected */
#define NWAY_AR_NEXT_PAGE		0x8000	/* Next Page ability supported */

/* Link Partner Ability Register (Base Page) */
#define NWAY_LPAR_SELECTOR_FIELD	0x0000	/* LP protocol selector field */
#define NWAY_LPAR_10T_HD_CAPS		0x0020	/* LP is 10T   Half Duplex Capable */
#define NWAY_LPAR_10T_FD_CAPS		0x0040	/* LP is 10T   Full Duplex Capable */
#define NWAY_LPAR_100TX_HD_CAPS	0x0080	/* LP is 100TX Half Duplex Capable */
#define NWAY_LPAR_100TX_FD_CAPS	0x0100	/* LP is 100TX Full Duplex Capable */
#define NWAY_LPAR_100T4_CAPS		0x0200	/* LP is 100T4 Capable */
#define NWAY_LPAR_PAUSE			0x0400	/* LP Pause operation desired */
#define NWAY_LPAR_ASM_DIR		0x0800	/* LP Asymmetric Pause Direction bit */
#define NWAY_LPAR_REMOTE_FAULT		0x2000	/* LP has detected Remote Fault */
#define NWAY_LPAR_ACKNOWLEDGE		0x4000	/* LP has rx'd link code word */
#define NWAY_LPAR_NEXT_PAGE		0x8000	/* Next Page ability supported */

/* Autoneg Expansion Register */
#define NWAY_ER_LP_NWAY_CAPS		0x0001	/* LP has Auto N