boot.s

strongarm的bootloader

 	B       InitUartEnable

Memclk60MHzInitUart:    	
	/*; Write H_UBRLCR,L_UBRLCR,MUBRLCR to set up comm parameters*/
	/*; Note: MUST UPDATE IN THIS ORDER! (see sec. 6.6.5 in 21285 databook)*/
	MOV	r0,#UART_L_UBRLCR_60MHZ
	STR	r0,[r1,#L_UBRLCR_REG]
	MOV	r0,#UART_M_UBRLCR_60MHZ
	STR	r0,[r1,#M_UBRLCR_REG]
	MOV	r0,#UART_H_UBRLCR
	STR	r0,[r1,#H_UBRLCR_REG]
 	B       InitUartEnable

InitUartEnable:	
	/*; set enable bit in UARTCON register*/
	MOV	r0,#1
	STR	r0,[r1,#UARTCON_REG]

	MOV	pc, lr		/* All done, return*/

	/*
	;; ********************************************************************
	;; PrintHexNibble -- prints the least-significant nibble in R0 as a
	;; hex digit
        ;;   Reads r0, writes r0 with RXSTAT, modifies r0,r1,r2
	;;   Falls through to PrintChar
	;; ********************************************************************
	*/
PrintHexNibble:	
	LDR	r1, ADDR_HEX_TO_ASCII_TABLE
	AND	r0, r0, #0xF
	LDR	r0, [r1,r0]	/* convert to ascii */
				/* fall through to PrintChar*/
	/*
	;; ********************************************************************
	;; PrintChar -- prints the character in R0
        ;;   Reads r0, writes r0 with RXSTAT, modifies r0,r1,r2
	;;********************************************************************
	*/
PrintChar:	
	MOV	r1, #CSR_BASE
TXBusy:	
        LDR     r2,[r1,#UARTFLG_REG]/* check status*/
	TST     r2,#UART_TX_FIFO_BUSY
        BNE     TXBusy
	STR	r0,[r1,#UARTDR_REG]
	LDR     r0,[r1,#UARTFLG_REG]
        MOV     pc, lr

	/*
        ;; ********************************************************************
	;; PrintWord -- prints the 4 characters in R0
        ;;   Reads r0, writes r0 with RXSTAT, modifies r1,r2,r3,r4
	;; ********************************************************************
	*/
PrintWord:	
	MOV	r3, r0
	MOV     r4, lr
	BL      PrintChar     
	
	MOV     r0,r3,LSR #8    /* shift word right 8 bits*/
	BL      PrintChar
	
	MOV     r0,r3,LSR #16   /* shift word right 16 bits*/
	BL      PrintChar
	
	MOV     r0,r3,LSR #24   /* shift word right 24 bits*/
	BL      PrintChar

	MOV	r0, #'\r'
	BL	PrintChar

	MOV	r0, #'\n'
	BL	PrintChar
	
        MOV     pc, r4

	/*
        ;; ********************************************************************
	;; PrintHexWord -- prints the 4 bytes in R0 as 8 hex ascii characters
	;;   followed by a newline
        ;;   Reads r0, writes r0 with RXSTAT, modifies r1,r2,r3,r4
	;; ********************************************************************
	*/
PrintHexWord:	
	MOV     r4, lr
	MOV	r3, r0
	MOV	r0, r3,LSR #28
	BL      PrintHexNibble     
	MOV	r0, r3,LSR #24
	BL      PrintHexNibble     
	MOV	r0, r3,LSR #20
	BL      PrintHexNibble     
	MOV	r0, r3,LSR #16
	BL      PrintHexNibble     
	MOV	r0, r3,LSR #12
	BL      PrintHexNibble     
	MOV	r0, r3,LSR #8
	BL      PrintHexNibble     
	MOV	r0, r3,LSR #4
	BL      PrintHexNibble     
	MOV	r0, r3
	BL      PrintHexNibble     

	MOV	r0, #'\r'
	BL	PrintChar

	MOV	r0, #'\n'
	BL	PrintChar

        MOV     pc, r4

	/*
	;; ********************************************************************
	;; copy - copies are region from addr in r0 to r1. r2=stopping point
	;; ********************************************************************
	*/
copy:	
	CMP	r1,r2
	LDRCC	r3,[r0],#4
	STRCC	r3,[r1],#4
	BCC	copy
	MOV	pc,lr

	/*
	;; ********************************************************************
	;; zi_init - initializes region starting at r1-r2 to r3
	;; ********************************************************************
	*/
zi_init:	
	CMP	r1,r2
	STRCC	r3,[r1],#4
	BCC	zi_init
	MOV	PC,lr

	/*
	;; ********************************************************************
	;; enableMMU
	;; ********************************************************************
	*/
ENTRY(enableMMU)
	/*; r0 = translation table base*/
	LDR	r0,DW_MMU_TABLE
	MCR	p15, 0, r0, c2, c0, 0

	/*; r0 = domain access control*/
	LDR	r0,MMU_DOMCTRL
	MCR	p15, 0, r0, c3, c0, 0


	/*; enable the MMU*/
	MRC	p15, 0, r0, c1, c0, 0
	ORR	r0, r0, #1      /* bit 0 of c1 is MMU enable*/
#ifdef CACHE_ENABLED	
	ORR	r0, r0, #4      /* bit 2 of c1 is DCACHE enable*/
	ORR	r0, r0, #8      /* bit 3 of c1 is WB enable*/
#endif	
	MCR	p15, 0, r0, c1, c0, 0

	/*
	;; flush the I/D caches
        ;;  c7 == cache control operation register
        ;;  crm==c7 opc2==0 indicates Flush I+D Cache
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c7, c7, 0x00
	/*
        ;; flush the I+D TLB
        ;;  c8 is TLB operation register
        ;;  crm=c7 opc2==0 indicates Flush I+D TLB
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c8, c7, 0x00 
	
	/*; return*/
	MOV	pc,lr		

	/*
	;; ********************************************************************
	;; flushTLB
	;; ********************************************************************
	*/
ENTRY(flushTLB)
	/*
	;; flush the I/D caches
        ;;  c7 == cache control operation register
        ;;  crm==c7 opc2==0 indicates Flush I+D Cache
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c7, c7, 0x00
	/*
        ;; flush the I+D TLB
        ;;  c8 is TLB operation register
        ;;  crm=c7 opc2==0 indicates Flush I+D TLB
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c8, c7, 0x00 
	
/*;; return*/
	MOV	pc,lr		
ENTRY(writeBackDcache)
	/*
	;; r0 points to the start of a 16384 byte region of readable 
	;; data used only for this cache flushingroutine. If this area 
	;; is to be used by other code, then 32K must be loaded and the
	;; flush MCR is not needed.
	/*

	/*; return:	 r0,r1,r2 trashed. data cache is clean*/
	add r1,r0,#32768
l1:	
	ldr r2,[r0],#32
	teq r1, r0
	bne l1
	mcr p15,0,r0,c7,c6,0
	mov pc,lr
	
ENTRY(readCPR1)
        MRC     p15,0,r0,c1,c0,0
        MOV     pc,lr
	
ENTRY(readCPR3)
        MRC     p15,0,r0,c3,c0,0
        MOV     pc,lr
	
	/*
	;; ********************************************************************
	;; boot - boots into another image. DOES NOT RETURN!
	;; r0 = pointer to bootinfo
	;; r1 = entry point of kernel
	;; ********************************************************************
	*/
ENTRY(boot)
	/*
        ;; flush the I+D TLB
        ;;  c8 is TLB operation register
        ;;  crm=c7 opc2==0 indicates Flush I+D TLB
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c8, c7, 0x00 /* flush I+D TLB */
        MCR     p15, 0, r0, c7, c10, 4 /* drain the write buffer*/

        /*; make sure the pipeline is emptied*/
        MOV     r0,r0
        MOV     r0,r0
        MOV     r0,r0
        MOV     r0,r0

	MOV	pc,r1		/* jump to addr. bootloader is done*/

	/*
	;; ********************************************************************
	;; bootLinux - boots into another image. DOES NOT RETURN!
	;; r0 = must contain a zero or else the kernel loops
        ;; r1 = architecture type (6 for old kernels, 17 for new)
	;; r2 = entry point of kernel
	;; ********************************************************************
	*/
ENTRY(bootLinux)
	/*
        ;; flush the I+D TLB
        ;;  c8 is TLB operation register
        ;;  crm=c7 opc2==0 indicates Flush I+D TLB
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c8, c7, 0x00 /* flush I+D TLB */
        MCR     p15, 0, r0, c7, c10, 4 /* drain the write buffer*/

	MOV     r3, #0x130
	MCR     p15, 0, r3, c1, c0, 0   /* disable the MMU */
        /*; make sure the pipeline is emptied*/
        MOV     r0,#0
        MOV     r0,r0
        MOV     r0,r0
        MOV     r0,r0

	MOV	pc,r2		/* jump to addr. bootloader is done*/

	.align 5
#ifdef HAS_REBOOT_COMMAND
	/* 
	 * remove reboot command until we make it *really* reboot
	 * things.  As it is, doesn't really work  or make much sense.
	 */
	/*
	;; ********************************************************************
	;; reboot - restarts the bootloader. DOES NOT RETURN!
	;; ********************************************************************
	*/
ENTRY(reboot)
       	/*; disable the instruction/data write buffer caches*/
	MRC	p15,0,r2,c1,c0,0
	MOV	r3,#~4
	AND	r2,r2,r3
	MOV	r3,#~8
	AND	r2,r2,r3
	MOV	r3,#~0x1000
	AND	r2,r2,r3
	MCR	p15,0,r2,c1,c0,0

	/*
	;; flush the caches
	;; flush the I/D caches
        ;;  c7 == cache control operation register
        ;;  crm==c7 opc2==0 indicates Flush I+D Cache
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c7, c7, 0x00
	/*
        ;; flush the I+D TLB
        ;;  c8 is TLB operation register
        ;;  crm=c7 opc2==0 indicates Flush I+D TLB
        ;;  r0 is ignored
	*/
	MCR	p15, 0, r0, c8, c7, 0x00
        MCR     p15, 0, r0, c7, c10, 4 /* drain the write buffer*/

        /*; make sure the pipeline is emptied*/
        MOV     r0,r0
        MOV     r0,r0
        MOV     r0,r0

	B	HiReset
#endif /* HAS_REBOOT_COMMAND */

	/*
	 * something that main calls
	 * what it wants ???
	 */
	
ENTRY(__main)
	mov	pc,lr		
	/*
	;; ********************************************************************
	;; Data Area
	;; ********************************************************************
	*/

	.align 2
CRC32POLY:	
	.word	0x04c11db7
	
	.align	2
addr_start:	
	.word	_C_FUNC(ResetEntryPoint)

	.align	2
SENSIBLE_SDRAM_TIMING_REGISTER:
	.word	SENSIBLE_SDRAM_TIMING_REGISTER_VAL

	.align	2
INITIAL_SDRAM_TIMING_REGISTER:
	.word	INITIAL_SDRAM_TIMING_REGISTER_VAL

	.align	2
ENTRY(HEX_TO_ASCII_TABLE)
	.ascii	"0123456789ABCDEF"

	.align	2
ADDR_HEX_TO_ASCII_TABLE:	
	.word	_C_FUNC(HEX_TO_ASCII_TABLE)

	.align	2
DW_STACK_STR:	
	.ascii	"STKP"

	.align	2
DW_GPIO_BASE:	
	.word   GPIO_BASE
	
	.align	2
DW_STACK_START:	
	.word	STACK_BASE+STACK_SIZE-4
	
	.align	2
DW_MMU_TABLE:	
	.word	MMU_TABLE_START

	.align	2
DW_USB_CONFIGURATION_BASE:	
	.word	USB_CONFIGURATION_BASE

	.align	2
DW_CACHE_FLUSH_REGION:	
	.word	CACHE_FLUSH_BASE
	
	.align	2
MMU_DOMCTRL:	
	.word	0xFFFFFFFF
DW_SDRAM_ARRAY0_ADDRSIZE:       
        .word	SDRAM_ARRAY0_ADDRSIZE	
DW_SDRAM_ARRAY1_ADDRSIZE:       
        .word	SDRAM_ARRAY1_ADDRSIZE	

	.align	2
STR_MTST:	
        .ascii	"MTST"
	.align	2
STR_MB2:	
        .ascii	"MBK2"
	.align	2
STR_ENDM:	
        .ascii	"ENDM"
	.align	2
	
STR_UNDEF:	
        .ascii	"UNDF"

	.align	2
STR_SWI:	
        .ascii  "SWI "

	.align	2
STR_PREFETCH_ABORT:	
        .ascii	"PABT"

	.align	2
STR_DATA_ABORT:	
        .ascii	"DABT"
	.word   0

	.align	2
STR_IRQ:	
        .ascii	"IRQ "

	.align	2
STR_FIQ:	
        .ascii	"FIQ"

	.align	2
STR_UNUSED:	
        .ascii  "UNSD"

	.align	2
STR_MEM_ERROR:
	.ascii	"DRAM ERROR"
	/*; ******************************************************************/