boot.s

strongarm的bootloader

	bl      PrintHexWord
	MOV	r0, #0x00080000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00100000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00200000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00400000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00800000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x01000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x02000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x04000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x08000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x10000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x20000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x40000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x80000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord

/*; debug print*/
DebugPrintAfterTestDram:        	
	LDR	r0, STR_ENDM
	BL      PrintWord

#ifdef NOTDEF
memTest:                        

        /* Initial - fill memory */
        mov     r0,#DRAM_BASE
        add     r1,r0,#DRAM_SIZE
	ldr     r2,CRC32POLY
	mov     r3,#-1
        mov     r4,#1

10:     orrs    r3,r4,r3,lsl#1
        eorcs   r3,r3,r2
        str     r3,[r0], #4
        mov     r6,r0
	mov     r7,r1
	mov     r8,r2
	mov     r9,r3
	mov     r10,r4
	bl      PrintHexWord
	mov     r0,r6
	mov     r1,r7
	mov     r2,r8
	mov     r3,r9
	mov     r4,r10
        cmp     r0,r1
        bne     10b

        /* Phase two, check */
        mov     r0,#DRAM_BASE
        mov     r3,#-1

20:     orrs    r3,r4,r3,lsl #1
        eorcs   r3,r3,r2
        ldr     r5,[r0],#4
        cmp     r5,r3
        bne     memError
        mov     r6,r0
	mov     r7,r1
	mov     r8,r2
	mov     r9,r3
	mov     r10,r4
	bl      PrintHexWord
	mov     r0,r6
	mov     r1,r7
	mov     r2,r8
	mov     r3,r9
	mov     r4,r10
        cmp     r0,r1
        bne     20b
	b	InitializePCI
	
memError:	
	LDR	r0, STR_MEM_ERROR
	BL      PrintWord
memError1:	
	B	memError1
#endif	
		
/*; Initialize PCI*/
InitializePCI:	
	BL	InitPCI

/*; debug print*/
	MOV	r0,#'*'
	BL      PrintChar

Enable5V:	
        /*; turn on 5V supply (to get the motor drivers into reset state ASAP -Jamey 1/3/99 */
        LDR     r0,DW_USB_CONFIGURATION_BASE
	LDR     r1,[r0,#0x50]      /* read current value*/
	BIC     r1,r1,#(1<<(3+16))
        STR     r1,[r0,#0x50]
	/*; enable I2C port, turn on both I2C bits*/
        LDR     r1,[r0,#0x4c]
        ORR     r1,r1,#(0x27 << 16)
        STR     r1,[r0,#0x4c]

/*; debug print*/
	MOV	r0,#'*'
	BL      PrintChar

#ifdef CACHE_ENABLED
	/*; Enable the Icache*/
#ifdef ICACHE_ENABLED	
	MRC	p15, 0, r0, c1, c0, 0
	ORR	r0, r0, #0x1000  /* bit 12 is ICACHE enable*/
	MCR	p15, 0, r0, c1, c0, 0
#endif

	/*; flush the I/D caches*/
        /*;  c7 == cache control operation register*/
        /*;  crm==c7 opc2==0 indicates Flush I+D Cache*/
        /*;  r0 is ignored*/
	MCR	p15, 0, r0, c7, c7, 0x00 
        /*; flush the I+D TLB*/
        /*;  c8 is TLB operation register*/
        /*;  crm=c7 opc2==0 indicates Flush I+D TLB*/
        /*;  r0 is ignored*/
	MCR	p15, 0, r0, c8, c7, 0x00 

	/*; Flush the data cache*/
	LDR	r0,DW_CACHE_FLUSH_REGION
	BL	_C_FUNC(writeBackDcache)
#endif	

/*; debug print*/
	MOV	r0,#'*'
	BL      PrintChar
	
#if 0	
	/*; clear all of SDRAM to 0*/
	MOV	r1,#0x00
	MOV	r2,#DRAM_SIZE
	MOV	r3,#0x00
	BL	zi_init
#endif	

	MOV	r0,#'%'
	BL      PrintChar
	
#ifdef CACHE_ENABLED
	/*; Flush the data cache*/
	LDR	r0,DW_CACHE_FLUSH_REGION
	BL	_C_FUNC(writeBackDcache)
#endif
	
	MOV	r0,#'*'
	BL      PrintChar
		
	/*; Get ready to call C functions*/
	LDR	r0, DW_STACK_STR
	BL	PrintWord
	LDR	r0, DW_STACK_START
	BL	PrintHexWord

ASENTRY(call_main)
	LDR	sp,DW_STACK_START
	MOV	fp,#0		/* no previous frame, so fp=0*/

	MOV	a1, #0		/* set argc to 0*/
	MOV	a2, #0		/* set argv to NUL*/
	BL	main		/* call main*/

	mov	pc, #FLASH_BASE	/* reboot */

	/*; *****************************************************************/
	/*; InitMem - initialize SDRAM*/
	/*; *****************************************************************/
ASENTRY(InitMem)

	/*
	;; SDRAM POWER ON SEQUENCE
	;; Mitsubishi M5M4V64Sx0 spec, page 13 
	
	;; Before starting normal operation, the following power on
	;; sequence is necessary to prevent a SDRAM from damaged or
	;; malfunctioning.
	;; 
	;; 1.Clock will be applied at power up along with
	;;    power. Attempt to maintain CKE high, DQM (x4,x8), DQMU/L
	;;    (x16) high and NOP condition at the inputs along with
	;;    power.
	;; 2. Maintain stable power, stable clock, and NOP input
	;;    conditions for a minimum of 200us.
	;; 3. Issue precharge commands for all banks. (PRE or PREA)
	;; 4. After all banks become idle state (after tRP), issue 8
	;;    or more auto-refresh commands.
	;; 5. Issue a mode register set command to initialize the mode
	;;    register.
	;; 
	;; After these sequence, the SDRAM is idle state and ready for
	;; normal operation.
	
	;; MAX708 power supervisor maintains reset for 200ms after
	;; poweron or reset switch.
	
	;; After reset, the SDRAM arrays are in an unknown state. To
	;; put them into a known state, force an all-banks precharge
	;; to each of the four possible arrays. You must access all
	;; four arrays for this even if all four are not fitted. This
	;; is necessary since the 21285 counts these precharge
	;; accesses, and inhibits access to the SDRAM until all four
	;; have been completed. Failure to perform four precharge
	;; access will result in unpredictable operation. An all-banks
	;; precharge is initiated by a read from any address in the
	;; mode register address space.
	*/
	MOV	r1,#DC21285_DRAM_A0MR	/* SDRAM array 0*/
	LDR	r0,[r1]			/* just read, don't care what returns*/
	ADD	r1,r1,#0x4000
	LDR	r0,[r1] /* SDRAM array 1*/
	ADD	r1,r1,#0x4000
	LDR	r0,[r1] /* SDRAM array 2*/
	ADD	r1,r1,#0x4000
	LDR	r0,[r1] /* SDRAM array 3*/


	/*
	;; Write to the SDRAM Timing Register. Set the refresh interval to the
	;; minimum because we have to wait for 8 refresh cycles to complete
	;; before we can rely on the SDRAMS operating normally.
	*/

	MOV	r1,#CSR_BASE
	LDR	r0,INITIAL_SDRAM_TIMING_REGISTER
	STR	r0,[r1,#SDRAM_TIMING]

	/*
	;; Wait for 8 refresh cycles to complete. The minimum refresh interval
	;; is 32 cycles and we are currently running with the Icache off, so
	;; the complete process will take 256 cycles (but make it 512)
	*/

	MOV	r0,#0x200
wait:	SUBS	r0,r0,#1
	BGT	wait

	/*
	;; Write to the SDRAM Mode Register. This requires one write operation
	;; for each SDRAM array. The address is important, not the data. The
	;; offset from the start of the mode space for each SDRAM array controls
	;; what data is written to the SDRAM mode register.
	*/


        MOV     r0,#0xFB
	MOV	r1,#(DC21285_DRAM_A0MR)
	STRB	r0,[r1,#((SDRAM_MODE_WM|SDRAM_MODE_LTMODE|SDRAM_MODE_BT|SDRAM_MODE_BL)<<2)]			/* doesn't matter what we write*/
        ADD     r1,r1,#0x4000     /*  DC21285_DRAM_A1MR*/
	STRB	r0,[r1,#((SDRAM_MODE_WM|SDRAM_MODE_LTMODE|SDRAM_MODE_BT|SDRAM_MODE_BL)<<2)]			
        ADD     r1,r1,#0x4000     /*  DC21285_DRAM_A2MR*/
	STRB	r0,[r1,#((SDRAM_MODE_WM|SDRAM_MODE_LTMODE|SDRAM_MODE_BT|SDRAM_MODE_BL)<<2)]			
        ADD     r1,r1,#0x4000     /*  DC21285_DRAM_A3MR*/
	STRB	r0,[r1,#((SDRAM_MODE_WM|SDRAM_MODE_LTMODE|SDRAM_MODE_BT|SDRAM_MODE_BL)<<2)]			

	/*
	;; Write to the four SDRAM Address and Size Registers. Note that we are
	;; NOT doing any kind of automatic memory detection and sizing here
	*/

	MOV     r1,#CSR_BASE
	LDR	r0,DW_SDRAM_ARRAY0_ADDRSIZE
	STR	r0,[r1,#SDRAM_ADDR_SIZE_0]
	LDR	r0,DW_SDRAM_ARRAY1_ADDRSIZE
	STR	r0,[r1,#SDRAM_ADDR_SIZE_1]
	MOV	r0,#SDRAM_ARRAY2_ADDRSIZE
	STR	r0,[r1,#SDRAM_ADDR_SIZE_2]
	MOV	r0,#SDRAM_ARRAY3_ADDRSIZE
	STR	r0,[r1,#SDRAM_ADDR_SIZE_3]

	/*
	;; Finally, reset the refresh interval to a sensible value. Continuing
	;; to run with a very short interval would waste memory bandwidth
	*/
	
	LDR	r0,SENSIBLE_SDRAM_TIMING_REGISTER
	STR	r0,[r1,#SDRAM_TIMING]

	MOV	pc, lr			/* All done, return*/

	/*
	;; ********************************************************************
	;; InitPCI - initialize PCI
	;; NOTE:	lr contains return address
	;;		a1 returns top of memory
	;; ********************************************************************
	;; This code does the bare minimum setup necessary to allow the PCI
	;; interface to be used.
	*/
ASENTRY(InitPCI)
	MOV	r1,#CSR_BASE

	MOV	r0,#0xC		/* disable outbound interrupts*/
	STR	r0,[r1,#PCI_OUT_INT_MASK]

	MOV	r0,#0		/* clear doorbell interrupts to PCI*/
	STR	r0,[r1,#DBELL_PCI_MASK]
	STR	r0,[r1,#DBELL_SA_MASK]	/* clear doorbell interrupts to SA110*/
	MOV     r0,#(0 << 15)
	STR	r0,[r1,#PCI_ADDR_EXT]	/* map PCI addr bit 31 to 0, as netbsd seems to expect -- Jamey 12/16/98*/

	MOV	r0,#SETUP_PCI_INT_ID	/* set int. ID=1 some sys can't handle 0*/
	STR	r0,[r1,#PCI_INT_LINE]   /* 21285 does not interpret this register*/

	LDR	r0,[r1,#SA_CONTROL]
	ORR	r0, r0,#PCI_NRESET	/* deassert PCI reset signal (page 7-51)*/
	/* leave these bits 0 -- set direction of xcs_l[2:0], used by PCI arbiter*/
	STR	r0,[r1,#SA_CONTROL]

	MOV	r0,#PCI_WINDOW_SIZE	/* open up window from PCI->SDRAM*/
	STR	r0,[r1,#DRAM_BASE_ADDR_MASK]
        MOV     r0,#0x00300000          /* 4MB expansion rom window size*/
        STR     r0,[r1,#ROM_BASE_ADDR_MASK]

	LDR	r0,[r1,#PCI_COMMAND]
	AND	r0,r0,#0		/* disable PCI for now, enabled below*/
	STR	r0,[r1,#PCI_COMMAND]
	LDR     r0,[r1,#PCI_COMMAND]     /* read PCI status register*/

	MOV	r0,#SZ_1G		/* CSR's appear much after DRAM  section 7.3.6, 7.1.11*/
	STR	r0,[r1,#PCI_CSR_MEM_BAR]
	MOV	r0,#0xf000		/* write 0xf000 to CSR I/O Base Addr Reg*/
	STR	r0,[r1,#PCI_IO_BAR]

	MOV	r0,#0			/* write 0x0 to SDRAM Base Addr. Reg.*/
	STR	r0,[r1,#PCI_DRAM_BAR]
	STR	r0,[r1,#MAILBOX_0]
	STR	r0,[r1,#MAILBOX_1]
	STR	r0,[r1,#MAILBOX_2]
	STR	r0,[r1,#MAILBOX_3]
	STR	r0,[r1,#DOORBELL_SETUP]

	/* Done: respond to I/O space & Memory transactions.*/
	/*	ALSO BE PCI MASTER*/
	MOV	r0, #PCI_CFN_INIT
	STR	r0, [r1, #PCI_COMMAND]

	/* Signal PCI_init_complete, won't hurt if it's already been done*/
	LDR	r0, [r1, #SA_CONTROL]
	ORR	r0, r0, #INIT_COMPLETE
	STR	r0, [r1, #SA_CONTROL]

	MOV	pc, lr			/* All done, return*/

	/*
	;; ********************************************************************
	;; InitUART - Initialize Serial Communications
	;; ********************************************************************
	;; Following reset, the UART is disabled. So, we do the following:
	*/
ASENTRY(InitUART)
	
	MOV	r1,#CSR_BASE
	ldr	r2,DW_GPIO_BASE
        MOV     r3,#FLASH_BASE
	
	/*; Program the UART control register*/
	MOV	r0,#0		/* disable UART completely, no HP SIR or IrDA*/
	STR	r0,[r1,#UARTCON_REG]

#if   (MEMCLK_HZ_OVERRIDE == 33333333)	
        B Memclk48MHzInitUart
#elif (MEMCLK_HZ_OVERRIDE == 48000000)	
        B Memclk48MHzInitUart
#elif (MEMCLK_HZ_OVERRIDE == 60000000)	
        B Memclk48MHzInitUart
#endif	

	/* first, check for existence of GPIO registers */
	ldr     r3, [r3, #0xC] /* contents of third word of flash */
	/* if SkiffV2, check Memclk speed in GPIO register 0 */
	ldr     r4, [r2, #0xC] /* possible GPIO contents */
        cmp     r3, r4
        beq     Memclk33MHzInitUart /* SkiffV1 -- no GPIO */
	and     r4, r4, #SYSTEM_REV_MEMCLK_MASK
        cmp     r4, #SYSTEM_REV_MEMCLK_48MHZ
	beq     Memclk48MHzInitUart
        cmp     r4, #SYSTEM_REV_MEMCLK_60MHZ
	beq     Memclk60MHzInitUart
	/* default to 33MHz */
Memclk33MHzInitUart:
	/*; Write H_UBRLCR,L_UBRLCR,MUBRLCR to set up comm parameters*/
	/*; Note: MUST UPDATE IN THIS ORDER! (see sec. 6.6.5 in 21285 databook)*/
	MOV	r0,#UART_L_UBRLCR_33MHZ
	STR	r0,[r1,#L_UBRLCR_REG]
	MOV	r0,#UART_M_UBRLCR_33MHZ
	STR	r0,[r1,#M_UBRLCR_REG]
	MOV	r0,#UART_H_UBRLCR
	STR	r0,[r1,#H_UBRLCR_REG]
 	B       InitUartEnable

Memclk48MHzInitUart:    	
	/*; Write H_UBRLCR,L_UBRLCR,MUBRLCR to set up comm parameters*/
	/*; Note: MUST UPDATE IN THIS ORDER! (see sec. 6.6.5 in 21285 databook)*/
	MOV	r0,#UART_L_UBRLCR_48MHZ
	STR	r0,[r1,#L_UBRLCR_REG]
	MOV	r0,#UART_M_UBRLCR_48MHZ
	STR	r0,[r1,#M_UBRLCR_REG]
	MOV	r0,#UART_H_UBRLCR
	STR	r0,[r1,#H_UBRLCR_REG]