boot.s

strongarm的bootloader

/****************************************************************************/
/* Copyright 2000 Compaq Computer Corporation.                              */
/*                                           .                              */
/* Copying or modifying this code for any purpose is permitted,             */
/* provided that this copyright notice is preserved in its entirety         */
/* in all copies or modifications.  COMPAQ COMPUTER CORPORATION             */
/* MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, AS TO THE USEFULNESS          */
/* OR CORRECTNESS OF THIS CODE OR ITS FITNESS FOR ANY PARTICULAR            */
/* PURPOSE.                                                                 */
/****************************************************************************/
/*	;; boot.s
	;; Compaq Personal Server Monitor Boot Code
        ;;      
        ;; Copyright 1999 Compaq Computer Corporation
        ;; All Rights Reserved
	;;
        ;; 
        ;; 
	;; This code is a very minimalist loader -- it jumps straight to
	;; main() after initalizing SDRAM,PCI,and the UART. =)
	;; boot.s from the Digital StrongARM uHAL provided inspiration for
	;; this loader.
*/
	
#ifdef __NetBSD__
#include <arm32/asm.h>
#else
#define __ASSEMBLY__	
#include <linux/linkage.h>
#define ASENTRY(x_) ENTRY(x_)        
#define _C_FUNC(x_) (/**/x_/**/)
#endif
#include "bootconfig.h"
#include "regs-21285.h"
	

/*;; memory layout and setup constants*/
#define SDRAM_TREF_MIN	(1<<16)		/*min refresh wait (1 cycle)*/
#define PCI_DRAMBASE	DRAM_BASE	/* PCI maps into kernel space*/
#define SETUP_PCI_INT_ID	0x1	/* Init PCI Interrupt ID=1*/
	
/*;; SA_CONTROL (0x13C) control register constants*/
#define INIT_COMPLETE	1
#define PCI_NRESET	0x200		/* when 1 and pci_cfn asserted,*/
					/* pci_rst_l deasserted*/
					/* (page 7-51)*/

#define INITIAL_SDRAM_TIMING_REGISTER_VAL	(SDRAM_TRP|SDRAM_TDAL|\
	SDRAM_TRCD|SDRAM_TCAS|\
	SDRAM_TRC|SDRAM_CMD_DRV_TIME|/*no parity*/|\
	SDRAM_SA110_PRIME|SDRAM_TREF_MIN)

#define SENSIBLE_SDRAM_TIMING_REGISTER_VAL	(SDRAM_TRP|SDRAM_TDAL|\
	SDRAM_TRCD|SDRAM_TCAS|\
        SDRAM_TRC|SDRAM_CMD_DRV_TIME|/*no parity*/|\
	SDRAM_SA110_PRIME|SDRAM_TREF)		
		
/*;; PCI Command Register*/
#define PCI_IO_ENABLE		0x0001
#define PCI_MEM_ENABLE		0x0002
#define PCI_MASTER_ENABLE	0x0004
#define PCI_MEM_WRINVALID	0x0010
#define PCI_PERR_ENABLE 	0x0020
#define PCI_SERR_ENABLE 	0x0080
#define PCI_FAST_B2B		0x0200
#define PCI_CFN_INIT		(PCI_IO_ENABLE|PCI_MEM_ENABLE | \
	                         PCI_MASTER_ENABLE|PCI_MEM_WRINVALID | \
                                 PCI_PERR_ENABLE|PCI_SERR_ENABLE)



	
	/*; *************************/
	/*; Start of executable code*/
	/*; *************************/
	/*
	 * due to being an a.out, this is really offset 0x20 past the
	 * load address
	 * The first 32bits is patched to be a jump around the
	 * a.out header
	 */
ASENTRY(_start)	
ENTRY(ResetEntryPoint)
	
	/*; switch to high memory (since 21285 aliases to 0 from 0x4100)*/
	/*; Loading pc with HiReset makes sure we are running from real rom,*/
	/*; instead of a shadowed address. The 1st write after reset switches*/
	/*; the memory map for normal operation*/
	B	HiReset
	
UndefEntryPoint:	
	B	HandleUndef
	
SWIEntryPoint:	
	B	HandleSWI
	
PrefetchAbortEntryPoint:	
	B	HandlePrefetchAbort
	
DataAbortEntryPoint:	
	B	HandleDataAbort
	
NotUsedEntryPoint:      	
	b       HandleNotUsed
IRQEntryPoint:	
	B	HandleIRQ
	
FIQEntryPoint:	
	B	HandleFIQ
	
/* 0x20:        */	
	.long   BOOTLDR_MAGIC       /* magic number so we can verify that we only put bootldr's into flash in the bootldr region */
/* 0x24:        */	
	.long   BOOTLDR_VERSION
/* 0x28:        */	
        .long   _start              /* where this bootldr was linked, so we can put it in memory in the right place */
	
HandleUndef:	
	mov	r0, #0
	str	r14, [r0, #0x0]
	mrc	p15, 0, r1, c6, c0, 0 /* fault address */
	str	r1, [r0, #0x4]
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	ldr	r0,STR_UNDEF
	BL	PrintWord
	B	WaitForInput
	
HandleSWI:	
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	LDR	r0,STR_SWI
	BL	PrintWord
	B	WaitForInput
	
HandlePrefetchAbort:	
	mov	r0, #0
	str	r14, [r0, #0x0]
	mrc	p15, 0, r1, c6, c0, 0 /* fault address */
	str	r1, [r0, #0x4]
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	LDR	r0,STR_PREFETCH_ABORT
	BL	PrintWord
	B	WaitForInput
	
HandleDataAbort:	
	mov	r0, #0
	str	r14, [r0, #0x0]
	mrc	p15, 0, r1, c6, c0, 0 /* fault address */
	str	r1, [r0, #0x4]
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	LDR	r0,STR_DATA_ABORT
	MOV	r1, r14
	BL	PrintWord
	B	WaitForInput
	
HandleIRQ:	
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	LDR	r0,STR_IRQ
	BL	PrintWord
	B	WaitForInput
	
HandleFIQ:	
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	LDR	r0,STR_FIQ
	BL	PrintWord
	B	WaitForInput
	
HandleNotUsed:	
	ORR	pc,pc,#FLASH_BASE/* jump to Flash*/
	LDR	r0,STR_UNUSED
	BL	PrintWord
	B	WaitForInput

WaitForInput:	
	MOV	r1,#CSR_BASE
	LDR	r0,[r1,#UARTFLG_REG]
	TST	r0,#UART_RX_FIFO_EMPTY
	BNE	WaitForInput
	
ConsumeInput:	
	MOV	r1,#CSR_BASE
	LDR	r2,[r1,#UARTDR_REG]
	LDR	r0,[r1,#UARTFLG_REG]
	TST	r0,#UART_RX_FIFO_EMPTY
	BEQ	ConsumeInput
	
HiReset:	
	ORR	pc,pc,#FLASH_BASE/* make sure we're in Flash memory space*/
	MOV     r0,#DRAM_SIZE
	STR	r0,[r0,#-1]

	/*; Turn off all interrupts*/
	/*; page 7-61*/
	MOV	r1, #CSR_BASE
	MOV     r0, #0xFFFFFFFF	/* into r0 to clear all interrupt enables*/
	STR	r0, [r1, #IRQ_ENABLE_CLEAR_REG]
	STR	r0, [r1, #FIQ_ENABLE_CLEAR_REG]

	
	/*; see 7-38 of the 21285 spec */
	/*; faster flash speed.*/

	LDR	r0,[r1,#SA_CONTROL]
	ORR	r0,r0,#(FLASH_ACCESS_TIME<<16)
	ORR	r0,r0,#(FLASH_BURST_TIME<<20)
	ORR	r0,r0,#(FLASH_TRISTATE_TIME<<24)
	STR	r0,[r1,#SA_CONTROL]

	/*; Initialize Serial UART*/
	BL	InitUART
	
/*; debug print*/
	MOV	r0,#'\r'
	BL      PrintChar
	MOV	r0,#'\n'
	BL      PrintChar
	MOV	r0,#'*'
	BL      PrintChar
	MOV	r0,#'$'
	BL      PrintChar
		
	/*; Initialize SDRAM*/
	BL	InitMem
	
	LDR     r0, STR_MTST
	BL      PrintWord

TestDram:       	
	/* some test code */
	MOV	r5, #0
	MOV	r0, #0x00000001
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000002
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000004
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000008
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000010
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000020
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000040
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000080
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000100
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000200
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000400
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000800
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00001000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00002000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00004000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00008000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00010000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00020000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00040000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00080000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00100000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00200000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00400000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00800000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x01000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x02000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x04000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x08000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x10000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x20000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x40000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x80000000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord

	LDR	r0, STR_MB2
	BL      PrintWord
	
TestDramBank2:       	
	/* some test code */
	MOV	r5, #0x1000000
	MOV	r0, #0x00000001
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000002
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000004
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000008
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000010
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000020
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000040
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000080
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000100
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000200
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000400
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00000800
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00001000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00002000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00004000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00008000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00010000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00020000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]
	bl      PrintHexWord
	MOV	r0, #0x00040000
	STR	r0, [r5, #48]
	LDR	r0, [r5, #48]