btpci.c

strongarm的bootloader

     putstr("\r\nMapping Registers Configured\r\n");
   }
   break;

   case CCB_POWER: {
      putLabeledWord("PowerControl: ", readInt8(socketOperationPhysAddr, 0x802));
      putLabeledWord("MiscCtl1[3Vbit1]: ", readInt8(socketOperationPhysAddr, 0x816));
      showRegs("Cardbus", (volatile dword *)socketOperationPhysAddr, cardbusRegDescrs);
      putstr("\r\n");

      /* turn on the power */
      putstr("turning on the power: ... "); putHexInt32(socketOperationPhysAddr[9]); 

      if (readInt8(socketOperationPhysAddr, 9) & 8) {
         /* 3.3V card */
         if (0) bset8(socketOperationPhysAddr, 0x10, (3 << 4));
         writeInt8(socketOperationPhysAddr, 0x816, 1); /* 3V card */
         putstr("  3.3V card\r\n");
      }
      if (readInt8(socketOperationPhysAddr, 9) & 4) {
         /* 5V card */
         if (0) bset8(socketOperationPhysAddr, 0x10, (2 << 4));
         writeInt8(socketOperationPhysAddr, 0x816, 0); /* 5V card */
         putstr("  5V card\r\n");
      }
      
      /* turn on power and enable the card */
      writeInt8(socketOperationPhysAddr, 0x802, 0x10);
      {
         int i;
         /* delay loop */
         for (i = 0; i < 1000; i++)
            writeInt8(socketOperationPhysAddr, 0x802, 0x10);
      }

      /* turn on power and enable the card */
      writeInt8(socketOperationPhysAddr, 0x802, 0x90);
      writeInt8(socketOperationPhysAddr, 0x803, 0x60);

      putstr("  done\r\n");
   } break;

   case CCB_REGS: {
     showRegs("PCIConf", (volatile dword *)socketConfig, pciConfigRegDescrs);
     putstr("\r\n");
     showRegs("Cardbus", (volatile dword *)socketOperationPhysAddr, cardbusRegDescrs);
     putstr("\r\n");
     showRegs("   exCa", (volatile dword *)(socketOperationPhysAddr+0x800), 
	      excaRegDescrs);
     putstr("\r\n");
   
   }
   break;

   case CCB_RESET_CARD: {
     putstr("Issuing card reset\r\n");
     {
       int i;
       bclr8(socketOperationPhysAddr, 0x803, 0x40);
       /* delay 20 ms */
       for (i = 0; i < 200 * 1000 * 20; i++)
	 /* spin */;
       /* turn off reset */
       bset8(socketOperationPhysAddr, 0x803, 0x40);
     }
   }
   break;

   case CCB_ENABLE_CARD: {
     putstr("Enabling card\r\n");
     {
       int i;
       bset8(socketOperationPhysAddr, 0x802, 0x80);
     }
   }
   break;

   case CCB_DISABLE_CARD: {
     putstr("Disabling card\r\n");
     {
       int i;
       bclr8(socketOperationPhysAddr, 0x802, 0x80);
     }
   }
   break;

   case CCB_CONFIGURATION_READ: {
     u_int32_t data[0x10];
     /* look at card registers */
     int i;
     for (i = 0; i < 0x40; i += 4) {
        data[i >> 2] = readInt32(cardPhysAddr, i);
     }
     for (i = 0; i < 0x40; i += 4) {
       putHexInt32((long)cardPhysAddr + i); putstr(":\t"); 
       putHexInt32(data[i>>2]);
       putstr("\r\n");
     }
   }
   case CCB_CONFIGURATION_WRITE: {
     u_int32_t data[0x10];
     /* look at card registers */
     int i;
     for (i = 0; i < 0x40; i += 4) {
        data[i >> 2] = readInt32(cardPhysAddr, i);
     }
     for (i = 0; i < 0x40; i += 4) {
       putHexInt32((long)cardPhysAddr + i); putstr(":\t"); 
       putHexInt32(data[i>>2]);
       putstr("\r\n");
     }
   }
   break;
   }
}
#endif

static void handleCirrusCardbusBridgeQuirks(struct PciConfigurationValues *pcv)
{
   volatile char *socketConfig = (volatile char *)makePCIConfigurationAddress(pcv->pciDevice, pcv->pciFunction, 0);
   long socketOperationPCIAddr = (long)readInt32(socketConfig,PCI_MAPREG_START);
   volatile byte *socketOperationPhysAddr = (volatile byte *)(((long)socketOperationPCIAddr)|0x80000000L);
   int socketNumber = readInt32(socketConfig, 0x4c);
   
   /* latency timer */
   bset32(socketConfig, 0x0c, 0x78 << 8);
   bset32(socketConfig, 0x18, 0x78 << 24);

   /* footbridge latency timers */
   bset32((char*)0x42000000, 0x0c, 0x78 << 8);

   /* bus numbers */
   writeInt32(socketConfig, 0x18, 
              (((1+socketNumber) << 16) /* subordinate bus number */
               | ((1+socketNumber) << 8) /* cardbus number */
               | (0 << 0) /* pci bus number */
               ));
#ifdef DeadCode
   /* memory range 0 */
   writeInt32(socketConfig, 0x1c, (long)socketOperationPCIAddr + 0x60000);     /* base */
   writeInt32(socketConfig, 0x20, (long)socketOperationPCIAddr + 0x70000 - 1); /* limit */
   /* memory range 1 */
   writeInt32(socketConfig, 0x24, (long)socketOperationPCIAddr + 0x70000);     /* base */
   writeInt32(socketConfig, 0x28, (long)socketOperationPCIAddr + 0x80000 - 1); /* limit */

   /* IO range 0 */
   writeInt32(socketConfig, 0x2c, 0x0);     /* base */
   writeInt32(socketConfig, 0x30, 255); /* limit */
   /* IO range 1 */
   writeInt32(socketConfig, 0x34, 256);     /* base */
   writeInt32(socketConfig, 0x38, 511); /* limit */
#endif

   bclr32(socketConfig, 0x3c, (1 << 26)); /* disable write posting, p58 of 6832 spec */

   /* setup legacy mode base address (IO space to talk to this controller), p62 of 6832 spec.*/
   writeInt32(socketConfig, 0x44, (0x3e0 + socketNumber) | /* inuse */ 0x01);

   /* power management register, p67 of PD6833 spec.*/
   if ((readInt32(socketConfig, 0x80) & 0xff) == 0x01) {
      /* supports power management */
      putLabeledWord("PowerManagementCapabilities: ", readInt32(socketConfig, 0x80));
      writeInt32(socketConfig, 0x84, 0x0);
   }

#ifdef Broken
   /* disable fifo's */
   bset32(socketOperationPhysAddr, 0x814, 0x6f << 24);
#endif

   /* device implementation byte A, p138 of 6832 spec */
   socketOperationPhysAddr[0x938] |= 0xf;

   /* configuring power control, pp128-129 of 6832 spec */
   socketOperationPhysAddr[0x926] = 0xa1;
   socketOperationPhysAddr[0x925] = 0xf;

#if 0
   putstr("\r\n");

   putLabeledWord("PowerControl: ", socketOperationPhysAddr[0x802]);
   putLabeledWord("MiscCtl1[3Vbit1]: ", socketOperationPhysAddr[0x816]);
   showRegs("Cardbus", (volatile dword *)socketOperationPhysAddr, cardbusRegDescrs);
   putstr("\r\n");

   putstr("\r\n");
   showRegs("PCIConf", (volatile dword *)socketConfig, pciConfigRegDescrs);
   putstr("\r\n");
   showRegs("Cardbus", (volatile dword *)socketOperationPhysAddr, cardbusRegDescrs);
   putstr("\r\n");
   showRegs("   exCa", (volatile dword *)(socketOperationPhysAddr+0x800), 
	    excaRegDescrs);
   putstr("\r\n");
#endif
   
}

static void handleOptiUSBControllerQuirks(struct PciConfigurationValues *pcv)
{
   /* some hacks to set up the USB controller properly */
   volatile dword *usbcfg = (volatile dword *)makePCIConfigurationAddress(pcv->pciDevice, pcv->pciFunction, 0);
   volatile dword *usbmem = (volatile dword *)(readInt32(usbcfg, PCI_MAPREG_START) | 0x80000000L);

   /* a hack to test connectivity to USB controller */
   writeInt32(usbcfg, 0x50, readInt32(usbcfg, 0x50) | (1 << 3)); /* enable writability of subsystem ID register */
   putstr("TSTUSB(");
   writeInt32(usbcfg, 0x2c, 0xAAAA5555L);
   putHexInt32(readInt32(usbcfg, 0x2c));
   putc(',');
   writeInt32(usbcfg, 0x2c, 0x5555AAAAL);
   putHexInt32(readInt32(usbcfg, 0x2c));
   putc(',');
   writeInt32(usbcfg, 0x2c, 0xFFFFFFFFL);
   putHexInt32(readInt32(usbcfg, 0x2c));
   putstr(")");

   /* cache size, latency timer */
   putstr("USBCSTM(");
   putHexInt32(readInt32(usbcfg, 0x0C));
   writeInt32(usbcfg, 0x0C, 0x0d08);
   putc(',');
   putHexInt32(readInt32(usbcfg, 0x0C));
   putc(')');

     /* setting the subsystem vendor ID register */
   writeInt32(usbcfg, 0x2C, 0xc8611045L);

   /* put the controller into reset state */
   putstr("USBHCCR[0](");
   putHexInt32(readInt32(usbmem, 0x4));
   writeInt32(usbmem, 0x4, 0);
   putc(',');
   putHexInt32(readInt32(usbmem, 0x4));
   putc(')');

     /* put it into reset state, in case it wasn't there */

           
     /* interrupt assignment and strap option overrides */
#if 1
   /* enable 5V supply on rev A skfmlb */

     /* disable all interrupts */
   writeInt32(usbmem, 0x14, 0x00);
   putstr("USBSTRP(");
   putHexInt32(readInt32(usbcfg, 0x50));
   writeInt32(usbcfg, 0x50, 0x00060108);
   putc(',');
   putHexInt32(readInt32(usbcfg, 0x50));
   putstr(")");
   writeInt32(usbcfg, 0x4c, 
	  ((1 << 16)  /* enable I2C port (test0/test1) */
	   | (3 << 17) /* drive a 1 on both outputs */
	   | (1 << 21) /* enable output */
	   ));

   writeInt32(usbmem, 0x48, readInt32(usbmem, 0x48) | 0x00000200);
#endif
   putstr("]");
}



void bootConfigurePCI(void)
{
   int i;
   /*   putstr("Configuring PCI\r\n");*/
   putstr("[");
   for (i = 0; i < 256; i++) {
      struct PciConfigurationValues *pcv = &pciConfigurationValues[i];
      byte *csrBase = (byte*)makePCIConfigurationAddress(pcv->pciDevice, pcv->pciFunction, 0);
      if (pcv->name == NULL)
         break;
      
#ifdef BTPCI_VERBOSE
      putstr("Configuring "); putstr(pcv->name); putstr("\r\n");
#endif /* BTPCI_VERBOSE */
      putstr(pcv->name);
      putstr("(");

      /* configure the interrupt register */
      *(volatile dword *)(csrBase+PCI_INTERRUPT_REG) = 
         (pcv->interruptPin << PCI_INTERRUPT_PIN_SHIFT)
         | (pcv->interruptLine << PCI_INTERRUPT_LINE_SHIFT);
#if BTPCI_DEBUG
      *(volatile dword *)(csrBase+PCI_MAPREG_START) = 0xFFFFFFFFL;
      putLabeledWord("   mapreg request: ",
		     *(volatile dword *)(csrBase+PCI_MAPREG_START));
      putHexInt32(*(volatile dword *)(csrBase+PCI_MAPREG_START)); putstr(",");
#endif

      /* configure base address registers */
      if (pcv->BAR0 != 0)
         *(volatile dword *)(csrBase+PCI_MAPREG_START) = pcv->BAR0;
      if (pcv->BAR1 != 0)
         *(volatile dword *)(csrBase+PCI_MAPREG_START+4) = pcv->BAR1;
      putstr(", MaxLat:"); putHexInt8(PCI_LATTIMER(readInt32(csrBase, PCI_BHLC_REG)));
      putstr(", MinGnt:"); putHexInt8((readInt32(csrBase, PCI_INTERRUPT_REG) >> 16) & 0xFF);
      bset32(csrBase, PCI_BHLC_REG, (0xFF << PCI_LATTIMER_SHIFT));

#if 1
      *(volatile dword *)(csrBase+PCI_COMMAND_STATUS_REG) = pcv->commandEnables;
#endif
#ifdef BTPCI_VERBOSE
      putLabeledWord("   cmdstatus: ",
		     *(volatile dword *)(csrBase+PCI_COMMAND_STATUS_REG));
#endif /* BTPCI_VERBOSE */
      putHexInt32(*(volatile dword *)(csrBase+PCI_COMMAND_STATUS_REG));
      putstr(",");
      
#ifdef BTPCI_VERBOSE
      putLabeledWord("   class: ", *(volatile dword *)(csrBase+PCI_CLASS_REG));
#endif /* BTPCI_VERBOSE */
      putHexInt32(*(volatile dword *)(csrBase+PCI_CLASS_REG));
      putstr(",");
      
#ifdef BTPCI_VERBOSE
      putLabeledWord("   mapreg: ", *(volatile dword *)(csrBase+PCI_MAPREG_START));
#endif /* BTPCI_VERBOSE */
      putHexInt32(*(volatile dword *)(csrBase+PCI_MAPREG_START));
      putstr(")");
      if (pcv->handleQuirks != NULL) {
         pcv->handleQuirks(pcv);
      }
   }
}




#define EEPROM_N_ABITS 6
#define EEPROM_N_DBITS 16

#define PCNET_RAP_WIO_REG 0x12
#define PCNET_RDP_WIO_REG 0x10
#define PCNET_BDP_WIO_REG 0x16
#define PCNET_RESET_WIO_REG 0x14

#define PCNET_RAP_DWIO_REG 0x14
#define PCNET_RDP_DWIO_REG 0x10
#define PCNET_BDP_DWIO_REG 0x1C
#define PCNET_RESET_DWIO_REG 0x18

static enum e_pcnet_io_mode {
  PCNET_UNKNOWN_MODE = 0,
  PCNET_WIO_MODE = 1,
  PCNET_DWIO_MODE = 2
} pcnet_io_mode = PCNET_DWIO_MODE;

static void pcnet_determine_io_mode(char *ioaddr)
{
  int csr0;
  int readback;

  return;
  writeInt16(ioaddr, PCNET_RAP_WIO_REG, 0);
  csr0 = readInt16(ioaddr, PCNET_RDP_WIO_REG);
  writeInt16(ioaddr, PCNET_RAP_WIO_REG, 88);
  readback = readInt16(ioaddr, PCNET_RAP_WIO_REG);
  if (csr0 == 4 && readback == 88) {
    pcnet_io_mode = PCNET_WIO_MODE;
    return;
  }
  putLabeledWord("csr0: ", csr0);
  putLabeledWord("readback: ", readback);

  writeInt32(ioaddr, PCNET_RAP_DWIO_REG, 0);
  csr0 = readInt32(ioaddr, PCNET_RDP_DWIO_REG)&0xFFFF;
  writeInt32(ioaddr, PCNET_RAP_DWIO_REG, 88);
  readback = readInt32(ioaddr, PCNET_RAP_DWIO_REG)&0xFFFF;
  if (csr0 == 4 && readback == 88) {
    pcnet_io_mode = PCNET_DWIO_MODE;
    return;
  }

  putLabeledWord("csr0: ", csr0);
  putLabeledWord("readback: ", readback);
  putstr("unknown pcnet io mode\r\n");
}

/* assumes WIO mode, which is the default mode of the PCNet controller after reset */
static void pcnet_write_csr (char *ioaddr, int regnum, int regval)
{
  writeInt32(ioaddr, PCNET_RAP_DWIO_REG, regnum);
  writeInt32(ioaddr, PCNET_RDP_DWIO_REG, regval&0xFFFF);
}

static int pcnet_read_csr (char *ioaddr, int regnum)
{
  writeInt32(ioaddr, PCNET_RAP_DWIO_REG, regnum);
  return readInt32(ioaddr, PCNET_RDP_DWIO_REG)&0xFFFF;
}

/* assumes WIO mode, which is the default mode of the PCNet controller after reset */
static void pcnet_write_bcr (char *ioaddr, int regnum, int regval)
{
  writeInt32(ioaddr, PCNET_RAP_DWIO_REG, regnum);
  writeInt32(ioaddr, PCNET_BDP_DWIO_REG, regval&0xFFFF);
}

static int pcnet_read_bcr (char *ioaddr, int regnum)
{
  writeInt32(ioaddr, PCNET_RAP_DWIO_REG, regnum);
  return readInt32(ioaddr, PCNET_BDP_DWIO_REG)&0xFFFF;