📄 top_avr_core_v7.vhd_altera
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end generate;
PORTB_Not_Impl:if not CImplPORTB generate
portb <= (others => 'Z');
end generate;
-- ************************************************
-- Unused IRQ lines
core_irqlines(7 downto 0) <= ( others => '0');
core_irqlines(13 downto 10) <= ( others => '0');
core_irqlines(21) <= '0';
-- ************************
-- Unused out_en
io_port_out_en(6 to 15) <= (others => '0');
-- UART
UARTImplemented:if CImplUART generate
UART_Iinst:component uart port map(
-- AVR Control
ireset => nrst_cp2,
cp2 => clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => uart_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => uart_out_en,
--UART
rxd => rxd,
rx_en => uart_rx_en,
txd => txd,
tx_en => uart_tx_en,
--IRQ
txcirq => core_irqlines(19), -- UART TX Comleet Handler ($0028)
txc_irqack => ind_irq_ack(19),
udreirq => core_irqlines(18), -- UART Empty ($0026)
rxcirq => core_irqlines(17) -- UART RX Comleet Handler ($0024)
);
-- UART connection to the external multiplexer
io_port_out(2) <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;
end generate;
UARTNotImplemented:if not CImplUART generate
txd <= 'Z';
uart_rx_en <= '0';
uart_tx_en <= '0';
end generate;
--****************** Timer/Counter **************************
TmrCnt_Impl:if CImplTmrCnt generate
TmrCnt_Inst:component Timer_Counter port map(
-- AVR Control
ireset => nrst_cp2,
cp2 => clk,
cp2en => cp2en,
tmr_cp2en => tmr_cp2en,
stopped_mode => stopped_mode,
tmr_running => tmr_running,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => tc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => tc_out_en,
-- External inputs/outputs
EXT1 => SBitZero,
EXT2 => SBitZero,
OC0_PWM0 => open,
OC1A_PWM1A => open,
OC1B_PWM1B => open,
OC2_PWM2 => open,
-- Interrupt related signals
TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020)
TC0OvfIRQ_Ack => ind_irq_ack(15),
TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E)
TC0CmpIRQ_Ack => ind_irq_ack(14),
TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014)
TC2OvfIRQ_Ack => ind_irq_ack(9),
TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012)
TC2CmpIRQ_Ack => ind_irq_ack(8),
TC1OvfIRQ => open,
TC1OvfIRQ_Ack => SBitZero,
TC1CmpAIRQ => open,
TC1CmpAIRQ_Ack => SBitZero,
TC1CmpBIRQ => open,
TC1CmpBIRQ_Ack => SBitZero,
TC1ICIRQ => open,
TC1ICIRQ_Ack => SBitZero);
-- Timer/Counter connection to the external multiplexer
io_port_out(4) <= tc_dbusout;
io_port_out_en(4) <= tc_out_en;
end generate;
-- Watchdog is not implemented
wdtmout <= '0';
-- Reset generator
ResetGenerator_Inst:component ResetGenerator port map(
-- Clock inputs
cp2 => clk,
cp64m => SBitZero,
-- Reset inputs
nrst => nrst,
npwrrst => SBitOne,
wdovf => wdtmout,
jtagrst => JTAG_Rst,
-- Reset outputs
nrst_cp2 => nrst_cp2_tmp,
nrst_cp64m => nrst_cp64m_tmp,
nrst_clksw => nrst_clksw
);
GlobalResets:if CUseAltera generate
begin
GLOBAL_nrst_cp2_Inst:component GLOBAL port map (A_IN=> nrst_cp2_tmp, A_OUT=> nrst_cp2);
end generate;
NoGlobalResets:if not CUseAltera generate
begin
nrst_cp2 <= nrst_cp2_tmp;
end generate;
NoGlobaClock:if not CUseAltera generate
begin
core_cp2 <= core_cp2_tmp;
end generate;
ClockGatingDis:if not CImplClockSw generate
core_cp2 <= clk;
end generate;
-- ********************** JTAG and memory **********************************************
InsertLCELLs:if CUseAltera generate
begin
-- Only for Synplify
LCELL_DM:for i in ram_din'range generate
begin
LCELL_DM_Inst:component LCELL port map (A_IN=> ram_din(i), A_OUT=> ramdata_in_tmp(i));
end generate;
end generate;
NoInsertLCELLs:if not CUseAltera generate
begin
pm_din_tmp <= pm_din;
ramdata_in_tmp <= ram_din;
end generate;
-- Data memory(8-bit)
DRAM_Inst:component DataRAM generic map(RAMSize => CDRAMSize)
port map(
cp2 => clk,
address => core_ramadr(LOG2(CDRAMSize)-1 downto 0),
ramwe => core_ramwe,
din => ramdata_in_tmp,
dout => ram_dout
);
PMForSimulation:if not CPMSynth generate
LCELL_PM:for i in 7 downto 0 generate
begin
LCELL_PM_Inst:component LCELL port map (A_IN=> pm_adr(i), A_OUT=> pm_adr_tmp(i));
end generate;
pm_adr_tmp(15 downto 8) <= (others => '0');
prom_Inst:component prom port map(
address_in => pm_adr_tmp,
data_out => pm_dout
);
end generate;
PMForSynthesis:if CPMSynth generate
LCELL_PM:for i in pm_adr_tmp'range generate
begin
LCELL_PM_Inst:component LCELL port map (A_IN=> pm_adr(i), A_OUT=> pm_adr_tmp(i));
end generate;
PMH_Inst:component DataRAM generic map(RAMSize => CPRAMSize/2)
port map(
cp2 => clk,
address => pm_adr_tmp(LOG2(CPRAMSize/2)-1 downto 0),
ramwe => pm_h_we,
din => pm_din(15 downto 8),
dout => pm_dout(15 downto 8)
);
PML_Inst:component DataRAM generic map(RAMSize => CPRAMSize/2)
port map(
cp2 => clk,
address => pm_adr_tmp(LOG2(CPRAMSize/2)-1 downto 0),
ramwe => pm_l_we,
din => pm_din(7 downto 0),
dout => pm_dout(7 downto 0)
);
end generate;
-- ********************** JTAG and memory **********************************************
-- Sleep mode is not implemented
sleep_mode <= '0';
JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map(
-- AVR Control
ireset => nrst_cp2,
cp2 => core_cp2,
adr => core_adr,
ramadr => core_ramadr,
ramre => core_ramre,
ramwe => core_ramwe,
dbus_in => core_dbusout,
dbus_out => jtag_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => jtag_out_en,
-- Core control signals(!!!TBD!!! WDR - disable)
cp2en => cp2en,
valid_instr => valid_instr,
insert_nop => insert_nop,
block_irq => block_irq,
change_flow => change_flow,
tmr_cp2en => tmr_cp2en,
stopped_mode => stopped_mode,
tmr_running => tmr_running,
wdr_en => wdr_en,
sleep_mode => sleep_mode,
ctrlx => ctrlx,
-- JTAG related inputs/outputs
TRSTn => TRSTn, -- Optional
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO_Out,
TDO_OE => TDO_OE,
-- INTERNAL SCAN CHAIN
PC => core_pc,
Inst => core_inst,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr,
-- CPU reset
jtag_rst => JTAG_Rst
);
-- JTAG OCD module connection to the external multiplexer
io_port_out(3) <= jtag_dbusout;
io_port_out_en(3) <= jtag_out_en;
TDO <= TDO_Out when TDO_OE='1' else 'Z';
-- ********************** SMBus **********************************************
SMBusImplemented:if CImplSMBusMod generate
SMBusMod_Inst:component SMBusMod port map(
-- AVR Control
ireset => nrst_cp2,
cp2 => clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => smbui_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => smbui_out_en,
-- Slave IRQ
twiirq => core_irqlines(16),
-- Master IRQ
msmbirq => core_irqlines(20), -- $002A ADC
-- "Off state" timer IRQ
offstirq => core_irqlines(22), -- $002E Analog comparator
offstirq_ack => ind_irq_ack(22),
-- TRI control and data for the slave channel
sdain => sda,
sdaout => sdaout,
sdaen => sdaen,
sclin => scl,
sclout => sclout,
sclen => sclen,
-- TRI control and data for the master channel
msdain => msda,
msdaout => msdaout,
msdaen => msdaen,
msclin => mscl,
msclout => msclout,
msclen => msclen
);
-- SMBus connection(for the slave)
sda <= sdaout when sdaen='1' else 'Z';
scl <= sclout when sclen='1' else 'Z';
-- SMBus connection(for the master)
msda <= msdaout when msdaen='1' else 'Z';
mscl <= msclout when msclen='1' else 'Z';
-- SMBus connection to the external multiplexer
io_port_out(5) <= smbui_dbusout;
io_port_out_en(5) <= smbui_out_en;
end generate;
SMBusNotImplemented:if not CImplSMBusMod generate
sda <= 'Z';
scl <= 'Z';
msda <= 'Z';
mscl <= 'Z';
-- !!!TBD!!!
smbui_dbusout <= (others => '0');
smbui_out_en <= '0';
core_irqlines(16) <= '0';
core_irqlines(20) <= '0';
core_irqlines(22) <= '0';
end generate;
-- ********************** SMBus **********************************************
end Struct;
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