📄 top_avr_core_v8.vhd
字号:
cp2 => clk4M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portb_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portb_out_en,
-- External connection
portx => PortBReg,
ddrx => DDRBReg,
pinx => portb);
-- PORTB connection to the external multiplexer
io_port_out(1) <= portb_dbusout;
io_port_out_en(1) <= portb_out_en;
-- Tri-state control for PORTB
PortBZCtrl:for i in portb'range generate
portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
end generate;
end generate;
PORTB_Not_Impl:if not CImplPORTB generate
portb <= (others => 'Z');
end generate;
-- ************************************************
-- Unused IRQ lines
core_irqlines(7 downto 4) <= ( others => '0');
core_irqlines(3 downto 0) <= ( others => '0');
core_irqlines(13 downto 10) <= ( others => '0');
core_irqlines(16) <= '0';
core_irqlines(22 downto 20) <= ( others => '0');
-- ************************
-- Unused out_en
io_port_out_en(5 to 15) <= (others => '0');
io_port_out(5 to 15) <= (others => (others => '0'));
--****************** Timer/Counter **************************
TmrCnt_Impl:if CImplTmrCnt generate
TmrCnt_Inst:component Timer_Counter port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk4M, -- clk,
cp2en => vcc,
tmr_cp2en => vcc,
stopped_mode => gnd,
tmr_running => gnd,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => tc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => tc_out_en,
-- External inputs/outputs
EXT1 => gnd,
EXT2 => gnd,
OC0_PWM0 => open,
OC1A_PWM1A => open,
OC1B_PWM1B => open,
OC2_PWM2 => open,
-- Interrupt related signals
TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020)
TC0OvfIRQ_Ack => ind_irq_ack(15),
TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E)
TC0CmpIRQ_Ack => ind_irq_ack(14),
TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014)
TC2OvfIRQ_Ack => ind_irq_ack(9),
TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012)
TC2CmpIRQ_Ack => ind_irq_ack(8),
TC1OvfIRQ => open,
TC1OvfIRQ_Ack => gnd,
TC1CmpAIRQ => open,
TC1CmpAIRQ_Ack => gnd,
TC1CmpBIRQ => open,
TC1CmpBIRQ_Ack => gnd,
TC1ICIRQ => open,
TC1ICIRQ_Ack => gnd);
-- Timer/Counter connection to the external multiplexer
io_port_out(4) <= tc_dbusout;
io_port_out_en(4) <= tc_out_en;
end generate;
-- Watchdog is not implemented
wdtmout <= '0';
-- Reset generator
ResetGenerator_Inst:component ResetGenerator port map(
-- Clock inputs
cp2 => clk4M, -- clk,
cp64m => gnd,
-- Reset inputs
nrst => nrst,
npwrrst => vcc,
wdovf => wdtmout,
jtagrst => JTAG_Rst,
-- Reset outputs
nrst_cp2 => core_ireset,
nrst_cp64m => nrst_cp64m_tmp,
nrst_clksw => nrst_clksw
);
ClockGatingDis:if not CImplClockSw generate
-- core_cp2 <= clk;
core_cp2 <= clk4M;
end generate;
-- ********************** JTAG and memory **********************************************
-- ram_cp2_n <= not clk;
ram_cp2_n <= not clk4M;
FirsMemConfig:if C_OrgMemCfg generate
-- The first memory configuration (PM 16Kx16/DM 16Kx8)
-- Data memory(8-bit)
DRAM_Inst:component XDM16Kx8 port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(13 downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst:component XPM16Kx16 port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(13 downto 0),
din => pm_din,
dout => pm_dout,
weh => pm_h_we,
wel => pm_l_we
);
end generate;
SecondMemConfig:if not C_OrgMemCfg generate
-- The second memory configuration (PM 8Kx16/DM 32Kx8)
-- Data memory(8-bit)
DRAM_Inst:component XDM32Kx8 port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(14 downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst:component XPM8Kx16 port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(12 downto 0),
din => pm_din,
dout => pm_dout,
weh => pm_h_we,
wel => pm_l_we
);
end generate;
-- ********************** JTAG and memory **********************************************
-- Sleep mode is not implemented
sleep_mode <= '0';
JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
-- JTAG related inputs/outputs
TRSTn => TRSTn, -- Optional
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO_Out,
TDO_OE => TDO_OE,
-- From the core
PC => core_pc,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr,
-- CPU reset
jtag_rst => JTAG_Rst
);
-- JTAG OCD module connection to the external multiplexer
io_port_out(3) <= (others => '0');
io_port_out_en(3) <= gnd;
TDO <= TDO_Out when TDO_OE='1' else 'Z';
-- *******************************************************************************************************
-- DMA, Memory decoder, ...
-- *******************************************************************************************************
uart_Inst:component uart port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => uart_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => uart_out_en,
-- UART
rxd => rxd,
rx_en => open,
txd => txd,
tx_en => open,
-- IRQ
txcirq => core_irqlines(19),
txc_irqack => ind_irq_ack(19),
udreirq => core_irqlines(18),
rxcirq => core_irqlines(17)
);
-- UART connection to the external multiplexer
io_port_out(2) <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;
-- Arbiter and mux
ArbiterAndMux_Inst:component ArbiterAndMux port map(
--Clock and reset
ireset => core_ireset,
cp2 => core_cp2,
-- Bus masters
busmin => busmin,
busmwait => busmwait,
-- Memory Address,Data and Control
ramadr => mem_ramadr,
ramdout => mem_ram_dbus_in,
ramre => mem_ramre,
ramwe => mem_ramwe,
cpuwait => slv_cpuwait
);
-- cpuwait
slv_cpuwait <= '0';
-- Core connection
busmin(0).ramadr <= core_ramadr;
busmin(0).dout <= ram_din; -- !!!
busmin(0).ramre <= core_ramre;
busmin(0).ramwe <= core_ramwe;
core_cpuwait <= busmwait(0);
-- UART DMA connection
busmin(1).ramadr <= (others => '0');
busmin(1).dout <= (others => '0'); -- !!!
busmin(1).ramre <= gnd;
busmin(1).ramwe <= gnd;
udma_mack <= not busmwait(1);
-- AES DMA connection
busmin(2).ramadr <= (others => '0');
busmin(2).dout <= (others => '0');
busmin(2).ramre <= gnd;
busmin(2).ramwe <= gnd;
aes_mack <= not busmwait(2);
-- UART DMA slave part
slv_outs(0).dout <= (others => '0');
slv_outs(0).out_en <= gnd;
-- AES DMA slave part
slv_outs(1).dout <= (others => '0');
slv_outs(1).out_en <= gnd;
-- Memory read mux
MemRdMux_inst:component MemRdMux port map(
slv_outs => slv_outs,
ram_sel => ram_sel, -- Data RAM selection(optional input)
ram_dout => mem_ram_dbus_out, -- Data memory output (From RAM)
dout => mem_mux_out -- Data output (To the core and other bus masters)
);
-- Address decoder
RAMAdrDcd_Inst:component RAMAdrDcd port map(
ramadr => mem_ramadr,
ramre => mem_ramre,
ramwe => mem_ramwe,
-- Memory mapped I/O i/f
stb_IO => stb_IO,
stb_IOmod => stb_IOmod,
-- Data memory i/f
ram_we => ram_ramwe,
ram_ce => ram_ce,
ram_sel => ram_sel
);
-- Given for the purpose of test only
--RAM_Inst:component RAM generic map(RAMSize => CRAMSize)
-- port map(
-- cp2 => cp2,
-- ramadr => mem_ramadr(LOG2(CRAMSize)-1 downto 0),
-- din => mem_ram_dbus_in,
-- dout => mem_ram_dbus_out,
-- ramwe => ram_ramwe
-- );
end Struct;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -