📄 pm_fetch_dec.vhd
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--************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.6! (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 31.05.06
-- Modification:
-- Registered ramre/ramwe outputs
-- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
-- SLEEP and CLRWDT instructions support was added
-- V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
-- V-flag bug fixed (ADIW/SBIW)
-- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
-- Output alu_data_d_in[7..0] was removed.
-- Gloabal clock enable(cp2en) was added
-- cpu_busy(push/pop) + irq bug was fixed 14.07.05
-- BRXX+IRQ interaction was modified -> cpu_busy
-- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity pm_fetch_dec is port(
-- Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (5 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep
sleepi : out std_logic;
irqok : out std_logic;
--Watchdog
wdri : out std_logic;
-- ALU interface(Data inputs)
alu_data_r_in : out std_logic_vector(7 downto 0);
-- ALU interface(Instruction inputs)
idc_add_out : out std_logic;
idc_adc_out : out std_logic;
idc_adiw_out : out std_logic;
idc_sub_out : out std_logic;
idc_subi_out : out std_logic;
idc_sbc_out : out std_logic;
idc_sbci_out : out std_logic;
idc_sbiw_out : out std_logic;
adiw_st_out : out std_logic;
sbiw_st_out : out std_logic;
idc_and_out : out std_logic;
idc_andi_out : out std_logic;
idc_or_out : out std_logic;
idc_ori_out : out std_logic;
idc_eor_out : out std_logic;
idc_com_out : out std_logic;
idc_neg_out : out std_logic;
idc_inc_out : out std_logic;
idc_dec_out : out std_logic;
idc_cp_out : out std_logic;
idc_cpc_out : out std_logic;
idc_cpi_out : out std_logic;
idc_cpse_out : out std_logic;
idc_lsr_out : out std_logic;
idc_ror_out : out std_logic;
idc_asr_out : out std_logic;
idc_swap_out : out std_logic;
-- ALU interface(Data output)
alu_data_out : in std_logic_vector(7 downto 0);
-- ALU interface(Flag outputs)
alu_c_flag_out : in std_logic;
alu_z_flag_out : in std_logic;
alu_n_flag_out : in std_logic;
alu_v_flag_out : in std_logic;
alu_s_flag_out : in std_logic;
alu_h_flag_out : in std_logic;
-- General purpose register file interface
reg_rd_in : out std_logic_vector (7 downto 0);
reg_rd_out : in std_logic_vector (7 downto 0);
reg_rd_adr : out std_logic_vector (4 downto 0);
reg_rr_out : in std_logic_vector (7 downto 0);
reg_rr_adr : out std_logic_vector (4 downto 0);
reg_rd_wr : out std_logic;
post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : out std_logic;
reg_h_out : in std_logic_vector (15 downto 0);
reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z
reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
-- I/O register file interface
sreg_fl_in : out std_logic_vector(7 downto 0);
globint : in std_logic; -- SREG I flag
sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : in std_logic_vector(7 downto 0);
sph_out : in std_logic_vector(7 downto 0);
sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : in std_logic_vector(7 downto 0);
-- Bit processor interface
bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT
branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
sbi_st_out : out std_logic;
cbi_st_out : out std_logic;
idc_bst_out : out std_logic;
idc_bset_out : out std_logic;
idc_bclr_out : out std_logic;
idc_sbic_out : out std_logic;
idc_sbis_out : out std_logic;
idc_sbrs_out : out std_logic;
idc_sbrc_out : out std_logic;
idc_brbs_out : out std_logic;
idc_brbc_out : out std_logic;
idc_reti_out : out std_logic);
end pm_fetch_dec;
architecture RTL of pm_fetch_dec is
-- COPIES OF OUTPUTS
signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL
signal irqack_int : std_logic;
signal irqackad_int : std_logic_vector(irqackad'range);
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
-- NEW SIGNALS
signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
signal ram_adr_int : std_logic_vector (15 downto 0);
constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
-- LD/LDD/ST/STD SIGNALS
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
-- PROGRAM COUNTER SIGNALS
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
signal program_counter : std_logic_vector (15 downto 0);
signal program_counter_in : std_logic_vector (15 downto 0);
signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
signal pc_low : std_logic_vector (7 downto 0);
signal pc_high : std_logic_vector (7 downto 0);
signal pc_low_en : std_logic;
signal pc_high_en : std_logic;
signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED
signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED
signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT
signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE
signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE
-- STATE MACHINES SIGNALS
signal irq_start : std_logic;
signal nirq_st0 : std_logic;
signal irq_st1 : std_logic;
signal irq_st2 : std_logic;
signal irq_st3 : std_logic;
signal ncall_st0 : std_logic;
signal call_st1 : std_logic;
signal call_st2 : std_logic;
signal call_st3 : std_logic;
signal nrcall_st0 : std_logic;
signal rcall_st1 : std_logic;
signal rcall_st2 : std_logic;
signal nicall_st0 : std_logic;
signal icall_st1 : std_logic;
signal icall_st2 : std_logic;
signal njmp_st0 : std_logic;
signal jmp_st1 : std_logic;
signal jmp_st2 : std_logic;
signal ijmp_st : std_logic;
signal rjmp_st : std_logic;
signal nret_st0 : std_logic;
signal ret_st1 : std_logic;
signal ret_st2 : std_logic;
signal ret_st3 : std_logic;
signal nreti_st0 : std_logic;
signal reti_st1 : std_logic;
signal reti_st2 : std_logic;
signal reti_st3 : std_logic;
signal brxx_st : std_logic; -- BRANCHES
signal adiw_st : std_logic;
signal sbiw_st : std_logic;
signal nskip_inst_st0 : std_logic;
signal skip_inst_st1 : std_logic;
signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
signal skip_inst_start : std_logic;
signal nlpm_st0 : std_logic;
signal lpm_st1 : std_logic;
signal lpm_st2 : std_logic;
signal nelpm_st0 : std_logic;
signal elpm_st1 : std_logic;
signal elpm_st2 : std_logic;
--signal nsts_st0 : std_logic;
--signal sts_st1 : std_logic;
--signal sts_st2 : std_logic;
signal sts_st : std_logic;
--signal nlds_st0 : std_logic;
--signal lds_st1 : std_logic;
--signal lds_st2 : std_logic;
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