📄 vopt02i87t
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m255K313Z0 cModel TechnologyZ1 dC:\Project\Xilinx UARTT_optZ2 V<f`hYzNcz5Qng4H>?bd[@0Z3 04 16 3 work uart_transmitter rtl 0Z4 =1-001e4fbfc81b-499c254f-7d-11c0Z5 o-quiet -auto_acc_if_foreign -work workZ6 tExplicit 1Z7 OE;O;6.3j;37T_opt1Z8 VeTN36:RSRejF_MXQ8XSHQ0Z9 04 10 3 work uart_16750 rtl 1Z10 =1-001e4fbfc81b-499c257e-2ce-10e4R5R6R7T_opt2Z11 V34jL1OKXWd?LhQO4]<XWU0Z12 04 17 2 work tb_slib_clock_div tb 1Z13 =1-001e4fbfc81b-499c268f-242-1438R5R6R7Eslib_clock_divZ14 w1234969538Z15 DPx22 C:\Modeltech_6.3j\ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3Z16 DPx22 C:\Modeltech_6.3j\ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf232Z17 dC:\Project\Xilinx UART\UART2Z18 8C:/Project/Xilinx UART/UART2/slib_clock_div.vhdZ19 FC:/Project/Xilinx UART/UART2/slib_clock_div.vhdl0L29Z20 Vj6J0D_zH?n87IngaebPHn2Z21 OE;C;6.3j;37Z22 o-work work -2002 -explicitR6Z23 !s100 a:nTe;IYfcoNELk1iP[Fk0ArtlR15R16Z24 DEx33 C:\Project\Xilinx UART\UART2\work 14 slib_clock_div 0 22 j6J0D_zH?n87IngaebPHn232Mx2 22 C:\Modeltech_6.3j\ieee 14 std_logic_1164Mx1 22 C:\Modeltech_6.3j\ieee 11 numeric_stdl46L41Z25 VT<;kg<L?DQjJ?dNZW0=X?1R21R22R6Z26 !s100 c>Cg_m?Jef7J7Da6PUjni3Eslib_counterZ27 w1234969560Z28 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3Z29 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2R17Z30 8C:/Project/Xilinx UART/UART2/slib_counter.vhdZ31 FC:/Project/Xilinx UART/UART2/slib_counter.vhdl0L29Z32 VBhW1nLRNU]EL>iHQ2M8:O1R2132R22R6Z33 !s100 QegEggi<?E8QXKIYdSSCm1ArtlR28R29Z34 DEx4 work 12 slib_counter 0 22 BhW1nLRNU]EL>iHQ2M8:O1l48L46Z35 VZ]FQ3`HejV??=eVS;0HWk3R2132Z36 Mx2 4 ieee 14 std_logic_1164Z37 Mx1 4 ieee 11 numeric_stdR22R6Z38 !s100 FM4>__dN7dHz[f?4JYC_11Eslib_edge_detectZ39 w1234969577R28R29R17Z40 8C:/Project/Xilinx UART/UART2/slib_edge_detect.vhdZ41 FC:/Project/Xilinx UART/UART2/slib_edge_detect.vhdl0L28Z42 V[Il<@i6H]N7]>EGd`HJgY0R2132R22R6Z43 !s100 FnekX0FQgKM;F6P0<`L171ArtlR28R29Z44 DEx4 work 16 slib_edge_detect 0 22 [Il<@i6H]N7]>EGd`HJgY0l40L38Z45 VUKBgdF3Y<6:RLCmkco69l0R2132R36R37R22R6Z46 !s100 Y7F4eBdiI<Jj`HO]WVZDA0Eslib_fifoZ47 w1234969650R29R17Z48 8C:/Project/Xilinx UART/UART2/slib_fifo_cyclone2.vhdZ49 FC:/Project/Xilinx UART/UART2/slib_fifo_cyclone2.vhdl0L15Z50 VWP;R[OZE2V??8c`@cPCZL1R2132R22R6Z51 !s100 fX24R4H9YkdQ6F_65j3M61AalteraR29Z52 DEx4 work 9 slib_fifo 0 22 WP;R[OZE2V??8c`@cPCZL1l61L34Z53 V97A:VJ[fZ50cX2[USfVZ10R2132Z54 Mx1 4 ieee 14 std_logic_1164R22R6Z55 !s100 [H05[^`HU>C[CGN`AMBPS3ArtlR28R29Z56 DEx4 work 9 slib_fifo 0 22 jCmTzglfhefGA@54@:2N<2l59L48Z57 VR>3L^jVoh<Fc]H8AkYi=I1R2132R36R37R22R6Z58 FC:/Project/Xilinx UART/UART2/slib_fifo.vhdZ59 w1234969629Z60 8C:/Project/Xilinx UART/UART2/slib_fifo.vhdZ61 !s100 JB<JEXao7B>bDD=D5WYW;3Eslib_input_filterZ62 w1234969666R28R29R17Z63 8C:/Project/Xilinx UART/UART2/slib_input_filter.vhdZ64 FC:/Project/Xilinx UART/UART2/slib_input_filter.vhdl0L28Z65 V?j?GWC_b=jF@EcfX>g73z2R2132R22R6Z66 !s100 V5hkO9Zn;U[E[;XoHH^=]1ArtlR28R29Z67 DEx4 work 17 slib_input_filter 0 22 ?j?GWC_b=jF@EcfX>g73z2l43L41Z68 V4Xl3IJz5JG66l20jamJh30R2132R36R37R22R6Z69 !s100 G_MKF:NY`0V;[jgm?Q2e03Eslib_input_syncZ70 w1234969679R28R29R17Z71 8C:/Project/Xilinx UART/UART2/slib_input_sync.vhdZ72 FC:/Project/Xilinx UART/UART2/slib_input_sync.vhdl0L28Z73 V<8bBmcHV51kmVJF>jjkTX0R2132R22R6Z74 !s100 TZR9>:90D0NhF4<jTQAI70ArtlR28R29Z75 DEx4 work 15 slib_input_sync 0 22 <8bBmcHV51kmVJF>jjkTX0l39L37Z76 VP3f>UehU?^GQ=Xm80iBCm3R2132R36R37R22R6Z77 !s100 ?Y6[^[gNl7@g=6X<z]9M61Eslib_mv_filterZ78 w1234969691R28R29R17Z79 8C:/Project/Xilinx UART/UART2/slib_mv_filter.vhdZ80 FC:/Project/Xilinx UART/UART2/slib_mv_filter.vhdl0L29Z81 VGj?:6Y0kHo]W2aK=0Dd[N0R2132R22R6Z82 !s100 ?Fl6mCQGFSEni]OEW2J1Q1ArtlR28R29Z83 DEx4 work 14 slib_mv_filter 0 22 Gj?:6Y0kHo]W2aK=0Dd[N0l50L44Z84 VW?nlR1iYAH<>;i5OLMW`I3R2132R36R37R22R6Z85 !s100 obzmajT@iHOb=ORgfYn`f3Etb_slib_clock_divZ86 w1234970099Z87 DPx22 C:\Modeltech_6.3j\ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2Z88 DPx22 C:\Modeltech_6.3j\ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90R15R1632R17Z89 8C:/Project/Xilinx UART/UART2/slib_testbench.vhdZ90 FC:/Project/Xilinx UART/UART2/slib_testbench.vhdl0L7Z91 V^G8bDEoYUU6SlQM^znNVF0R21R22R6Z92 !s100 VQf80mZa4K`HJAKd@4VM=0AtbR24R87R88R15R16DEx33 C:\Project\Xilinx UART\UART2\work 17 tb_slib_clock_div 0 22 ^G8bDEoYUU6SlQM^znNVF032Mx4 22 C:\Modeltech_6.3j\ieee 14 std_logic_1164Mx3 22 C:\Modeltech_6.3j\ieee 11 numeric_stdMx2 22 C:\Modeltech_6.3j\ieee 18 std_logic_unsignedMx1 22 C:\Modeltech_6.3j\ieee 15 std_logic_arithl26L10Z93 VCcU^b41z11DmUBYVLE7AT3R21R22R6Z94 !s100 ^CciNAQRQ8fDVN3d700Z01Etb_slib_mv_filterR86Z95 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2Z96 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90R28R29R17R89R90l0L60Z97 Vmd4aCYD@3g9=i2fe_;B4J1R2132R22R6Z98 !s100 4^9A18ac]9o_ZokmnV_6[2AtbR95R96R28R29Z99 DEx4 work 17 tb_slib_mv_filter 0 22 md4aCYD@3g9=i2fe_;B4J1l83L63Z100 VzFDZM[e7nU_N^JnWLV?;Y2R2132Z101 Mx4 4 ieee 14 std_logic_1164Z102 Mx3 4 ieee 11 numeric_stdZ103 Mx2 4 ieee 18 std_logic_unsignedZ104 Mx1 4 ieee 15 std_logic_arithR22R6Z105 !s100 =J5DBM40C]A9nnX`HSWb01Etb_slib_shift_regR86R95R96R28R29R17R89R90l0L142Z106 V3[nHkZejb2H2SF4:]FnRd3R2132R22R6Z107 !s100 27SzLmD94]RhIb26U:Kae3AtbR95R96R28R29Z108 DEx4 work 17 tb_slib_shift_reg 0 22 3[nHkZejb2H2SF4:]FnRd3l167L145Z109 VRV4mzZHk>ROG1A`mTf3<M2R2132R101R102R103R104R22R6Z110 !s100 0]W9QRcL23_b`a8YUK<N42Euart_16750Z111 w1234969702R28R29R17Z112 8C:/Project/Xilinx UART/UART2/uart_16750.vhdZ113 FC:/Project/Xilinx UART/UART2/uart_16750.vhdl0L36Z114 VfLmIbH1HFCzWh3GBc^cVT0R2132R22R6Z115 !s100 H2B3BCzPOF67`WJI?VUDL2ArtlR28R29Z116 DEx4 work 10 uart_16750 0 22 fLmIbH1HFCzWh3GBc^cVT0l375L64Z117 V9m_hob2H<DRG4<gg>]0^n2R2132R36R37R22R6Z118 !s100 `j]NcCkCR7d>Uz?39cB[K1Euart_baudgenZ119 w1234969713R28R29R17Z120 8C:/Project/Xilinx UART/UART2/uart_baudgen.vhdZ121 FC:/Project/Xilinx UART/UART2/uart_baudgen.vhdl0L29Z122 VT6lio<HZ[jI9[UXXkSfVK0R2132R22R6Z123 !s100 hM6BHYV7H6RQ6dYXS>nfz1ArtlR28R29Z124 DEx4 work 12 uart_baudgen 0 22 T6lio<HZ[jI9[UXXkSfVK0l43L40Z125 V^hml_:_X4^NG>eb2de>aA0R2132R36R37R22R6Z126 !s100 k4EG_18TN=6B2`fS89F=H1Euart_interruptZ127 w1234969724R28R29R17Z128 8C:/Project/Xilinx UART/UART2/uart_interrupt.vhdZ129 FC:/Project/Xilinx UART/UART2/uart_interrupt.vhdl0L33Z130 V]I[G]YUFc_h<i1FgBC4zj1R2132R22R6Z131 !s100 ^b2Z:L]gS^VV5O_bR9DI;1ArtlR28R29Z132 DEx4 work 14 uart_interrupt 0 22 ]I[G]YUFc_h<i1FgBC4zj1l57L49Z133 VYFNYigCP<eXe?OH7om=kj0R2132R36R37R22R6Z134 !s100 M1kRoKQT=cNIQUJ@NV9Ce1Euart_receiverZ135 w1234969735R28R29R17Z136 8C:/Project/Xilinx UART/UART2/uart_receiver.vhdZ137 FC:/Project/Xilinx UART/UART2/uart_receiver.vhdl0L29Z138 VQY@:[^dZ9oof[Wd4T`9nR3R2132R22R6Z139 !s100 NJ`YljG7MJX4gP_dPcEaS1ArtlR28R29Z140 DEx4 work 13 uart_receiver 0 22 QY@:[^dZ9oof[Wd4T`9nR3l104L49Z141 VzE75HcI4@3ZNI:05b8iNW3R2132R36R37R22R6Z142 !s100 bGYMhU[k4<YlT0Kg]S>ZQ1Euart_transmitterZ143 w1234969747R28R29R17Z144 8C:/Project/Xilinx UART/UART2/uart_transmitter.vhdZ145 FC:/Project/Xilinx UART/UART2/uart_transmitter.vhdl0L29Z146 Vf0RUzRfclo=;1P@62gP=K2R2132R22R6Z147 !s100 53oC`SB[hQBI=jnNL3@Jk1ArtlR28R29Z148 DEx4 work 16 uart_transmitter 0 22 f0RUzRfclo=;1P@62gP=K2l59L48Z149 V>Se0V>n962ibBkPe:WfFR2R2132R36R37R22R6Z150 !s100 ozFhV7Yb1E9FWzLcC?EUV1⌨️ 快捷键说明
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