setup_sdram.asm

adi bf533视频编码程序

#include <defBF533.h>

#include "pll.h"

.global _setup_sdram;
.section L1_code;
/*****************************************************/
_setup_sdram:
[--sp]=rets;

	P0.L = LO(EBIU_AMGCTL);
	P0.H = HI(EBIU_AMGCTL);
	R0.L = W[P0];
	BITSET(R0, 8);
	W[P0] = R0;
	SSYNC;
		
#if defined(PLL_MSEL)  || defined(PLL_D)

	#ifdef PLL_LOCK_COUNT
		p0.l = lo(PLL_LOCKCNT);
		p0.h = hi(PLL_LOCKCNT);
        r0.l = lo(PLL_LOCK_COUNT);
		r0.h = hi(PLL_LOCK_COUNT);
		w[p0] = r0;
		ssync;
	#endif	//PLL_LOCK_COUNT

	p0.l = lo(PLL_CTL);
	p0.h = hi(PLL_CTL);
	r1 = w[p0](z);
	r2 = r1;
	r0 = 0(z);
		
	#ifdef PLL_D
		bitclr(r1,0);
		r0.l = (PLL_D & 0x1);
		r1 = r1 | r0;
	#endif // PLL_D
	
	#ifdef PLL_MSEL
		r0.l = 0x81ff;
		r1 = r1 & r0;
		r0.l = (PLL_MSEL & 0x3f) << 9;
		r1 = r1 | r0;
	#endif // PLL_MSEL
	
	cc = r1 == r2;       // check if PLL_CTL changed
	if cc jump skip_pll; // skip the PLL_CTL update
	
	p1.l = lo(SIC_IWR);  // enable PLL Wakeup Interrupt
	p1.h = hi(SIC_IWR);
	r0 = [p1];			
	bitset(r0,0);	  
	[p1] = r0;
	
	w[p0] = r1;          // Apply PLL_CTL changes.
	ssync;
	
	// Because I am in the reset routine
	// there is no need to disable(cli)/enable(sti)
	// interrupts.
	
	idle;	// wait for Loop_count expired wake up
	ssync; // (no ssync required).
	
#endif //(PLL_MSEL | PLL_D)
skip_pll:
    nop;
    nop;
    nop;
    nop;
//-------------------------------------
	
// Reconfigure PLL_DIV Register
// Can be done on the fly

#if defined(PLL_CSEL) || defined(PLL_SSEL)
	p0.l = lo(PLL_DIV);
	p0.h = hi(PLL_DIV);
	r1 = w[p0](z);
	r0 = 0(z);
	
	#ifdef PLL_CSEL
		r0.l = ~(0x3<<4);
		r1 = r1 & r0;
		r0.l = ((PLL_CSEL & 0x3)<<4);
		r1 = r1 | r0;
	#endif // PLL_CSEL
	
	#ifdef PLL_SSEL
		r0.l = ~(0xf);
		r1 = r1 & r0;
		r0.l = (PLL_SSEL & 0xf);
		r1 = r1 | r0;
	#endif // PLL_SSEL
	
	w[p0] =r1;
	ssync;
#endif //(PLL_CSEL | PLL_SSEL)




		/* Check whether SDRAM is enabled already.  If so, jump to done.
	   If not, continue with configurations.  */
	P0.l = lo(EBIU_SDSTAT);
	P0.h = hi(EBIU_SDSTAT);
	R0 = w[p0](z);
	CC = bittst(R0, bitpos(SDRS));  // SDRS
	if !CC jump done;
	
	
	/* Initalize SDRAM registers. */

	//SDRAM Refresh Rate Control Register
	
	P0.L = lo(EBIU_SDRRC);
	P0.H = hi(EBIU_SDRRC);
	R0 = 0x0817 (z);								
	w[P0] = R0;
	
	//SDRAM Memory Bank Control Register
	P0.L = lo(EBIU_SDBCTL);			
	P0.H = hi(EBIU_SDBCTL);					
	R0.L = 0x0013;								
	R0.H = 0x0000;								
	[P0] = R0;



	//SDRAM Memory Global Control Register	
	P0.L = lo(EBIU_SDGCTL);// & 0xffff;
	P0.H = hi(EBIU_SDGCTL);// >> 16;
	
	
	R0.L = 0x998d;
	R0.H = 0x0091;
	[P0] = R0;
	
		
done:	
	rets=[sp++];
	RTS;
	
	
_setup_sdram.END: