ez_kit_isr_config.asm

adi bf533视频编码程序

/******************************************************************************/
//
// Name: 	BF533 EZ-KIT video ITU-656 receive mode
//
/******************************************************************************

(C) Copyright 2003 - Analog Devices, Inc.  All rights reserved.

File Name:		BF533_EZ-KIT_ISR_Config.asm

Date Modified:	3/27/03		TL		Rev 1.2

Software:       VisualDSP++3.1

Hardware:		ADSP-BF533 EZ-KIT Board

Special Connections:  None

Purpose:		Interrupt priority and masking 
				
				
Program Parameters:

********************************************************************************/


#include <defBF533.h>

.global	_BF533_EZ_KIT_ISR_Config;

//.extern _DAG_RET_SR;
//.extern __inmem_dma_yuv_buffer_en;

//.extern _in_buffer1;
//.extern _in_buffer2;
//.extern _yuv_buffer0;
//.extern _yuv_buffer1;
//.extern _yuv_buffer_flag;
//.extern _mSourceHeight;
//.extern _mSourceWidth;
//.extern _mPtrY;
//.extern _mPtrU;
//.extern _mPtrV;
.extern _cur_dma_buf_i;
.extern _cur_enc_buf_i;
.extern _mPtr656;
//.extern _y0_config;
//.extern _y1_config;
//.extern DAG_SAVE;

//.section L1_data_a;
//.global _flag;
//.var _flag=0;


.section L1_code;
/*******************************************************************************/
_BF533_EZ_KIT_ISR_Config:
     [--sp]=(r7:4, p5:3);
     [--sp]=rets;
	//Link the DMA interrupt subroutine to the DSP interrupt event 8

	p0.h = hi(EVT8);
	p0.l = lo(EVT8);
    r0.l = PPI_DMA_ISR;
	r0.h = PPI_DMA_ISR; 	// IVG8 Handler
  	[p0] = r0;
	ssync;
	
  	p0.h = hi(SIC_RVECT);
	p0.l = lo(SIC_RVECT);
	//enables PPI DMA interrupt by setting the System Interrupt IMASK Register
	r0 = 0x0100(z);	
	r1 = [p0+SIC_IMASK-SIC_RVECT];
	r0 = r0 | r1;
	[p0+SIC_IMASK-SIC_RVECT] = r0;
	ssync;
	
	//The PPI DMA is linked to interrupt vector 8 IVG8
	r0 = P8_IVG(8)(z);
	r1 = [p0+SIC_IAR1-SIC_RVECT];
	r1 >>= 4;
	r1 <<= 4;
	r0 = r1 | r0;
	[p0+SIC_IAR1-SIC_RVECT] = r0;
	ssync;
	
    //Finally the DMA interrupt has been enabled at the core level
	p0.h = hi(IMASK);
	p0.l = lo(IMASK);
	
	r1 = [p0];	
	r0 = 0x0100;
	r0 = r0 | r1; 
	
	[p0] = r0;
	ssync;
	
	rets=[sp++];
	(r7:4, p5:3) = [sp++];
	
_BF533_EZ_KIT_ISR_Config.END:
RTS;


/******************************************************/
.extern _next_ppi_dma_desc;
.extern _next_dma_buf_i;
PPI_DMA_ISR:

        [--SP]=RETI;
//        [--SP]=RETS;
        [--SP]=(R7:0,P5:0);
//        [--SP]=I0;
//        [--SP]=I1;
//        [--SP]=I2;
//        [--SP]=I3;
//        [--SP]=M0;
//        [--SP]=M1;
//        [--SP]=M2;
//        [--SP]=M3;
//        [--SP]=B0;
//        [--SP]=B1;
//        [--SP]=B2;
//        [--SP]=B3;
//        [--SP]=L0;
//        [--SP]=L1 ;
//        [--SP]=L2;
//        [--SP]=L3 ;
//        [--SP]=LC0;
//        [--SP]=LC1;
       [--SP]=ASTAT;
       
	P0.H = HI(DMA0_NEXT_DESC_PTR);
	P0.L = LO(DMA0_NEXT_DESC_PTR);
	R0 = 0X1(Z);
	W[P0+DMA0_IRQ_STATUS-DMA0_NEXT_DESC_PTR] = R0; 
	SSYNC;
	
	P0.L = _next_dma_buf_i;
	P0.H = _next_dma_buf_i;
	R0 = [P0];
	
	P1.L = _cur_dma_buf_i;
	P1.H = _cur_dma_buf_i;
	[P1] = R0;
	
	R1 = R0;
	R1 += 1;
	R3 = 3;
	R1 = R1 & R3;
		
	P2.L = _cur_enc_buf_i;
	P2.H = _cur_enc_buf_i;
	R3 = [P2];
	CC = R1==R3;
	IF !CC JUMP not_catch;
	R1 = R0;
	
not_catch:
	[P0] = R1;
	R1 <<= 2;
	
	R0.L = _mPtr656;
	R0.H = _mPtr656;
	R2 = R0 + R1;
	P2 = R2;
	P0.L = _next_ppi_dma_desc;
	P0.H = _next_ppi_dma_desc;
	P1 = [P0];
	R1 = P1;
	R1.L = W[P1];
	[P0] = R1;						//update next desc;
	R1 += 2;
	P1 = R1;
	R2 = [P2];						//next buf start addr;
	W[P1++] = R2;
	W[P1] = R2.H;

	ASTAT=[SP++];
//	LC1=[SP++];
//	LC0=[SP++];
//	L3=[SP++];
//	L2=[SP++];
//	L1=[SP++];
//	L0=[SP++];
//	B3=[SP++];
//	B2=[SP++];
//	B1=[SP++];
//	B0=[SP++];
//	M3=[SP++];
//	M2=[SP++];
//	M1=[SP++];
//	M0=[SP++];
//	I3=[SP++];
//	I2=[SP++];
//	I1=[SP++];
//	I0=[SP++];

	(R7:0, P5:0)=[SP++];
//	RETS=[SP++];
	RETI=[SP++];

PPI_DMA_ISR.end:
	RTI;