📄 ppi_dma.asm
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#include "defBF533.h"
.section L1_data_b;
.align 4;
.global _ppi_dma_queue;
.byte2 _ppi_dma_queue[4 * 3];
.global _next_ppi_dma_desc;
.byte4 _next_ppi_dma_desc;
//.extern _cur_dma_buf_i;
//.extern _cur_enc_buf_i;
.extern _mPtr656;
.section L1_code;
.align 4;
.global _ppi_dma_ini;
_ppi_dma_ini:
[--SP] = RETS;
[--SP] = (R7:4, P5:3);
L0 = 0;
R0.L = _ppi_dma_queue;
R0.H = _ppi_dma_queue;
R3 = R0;
I0 = R3;
I2.L = _mPtr656;
I2.H = _mPtr656;
R3 += 6;
R2 = [I2++] || W[I0++] = R3.L;
R3 += 6;
W[I0++] = R2.L;
W[I0++] = R2.H;
R2 = [I2++] || W[I0++] = R3.L;
R3 += 6;
W[I0++] = R2.L;
W[I0++] = R2.H;
R2 = [I2++] || W[I0++] = R3.L;
R3 = R0;
W[I0++] = R2.L;
W[I0++] = R2.H;
R2 = [I2++] || W[I0++] = R3.L;
W[I0++] = R2.L;
W[I0++] = R2.H;
P0.L = _next_ppi_dma_desc;
P0.H = _next_ppi_dma_desc;
R0 += 6;
[P0] = R0;
(R7:4,P5:3) = [SP++];
RETS = [SP++];
_ppi_dma_ini.end:
RTS;
.global _ppi_dma_en;
_ppi_dma_en:
[--SP]=RETS;
[--SP] = (R7:0, P5:0);
//PPI DMA chanel
P0.H = HI(DMA0_NEXT_DESC_PTR);
P0.L = LO(DMA0_NEXT_DESC_PTR);
R7.L = _ppi_dma_queue; //Address of DMA Descriptor
R7.H = _ppi_dma_queue;
[P0] = R7;
SSYNC;
R0 = 720;
R1 = 2;
W[P0+DMA0_X_COUNT-DMA0_NEXT_DESC_PTR] = R0;
W[P0+DMA0_X_MODIFY-DMA0_NEXT_DESC_PTR] = R1;
R0 = 288;
R1 = 18;
W[P0+DMA0_Y_COUNT-DMA0_NEXT_DESC_PTR] = R0;
W[P0+DMA0_Y_MODIFY-DMA0_NEXT_DESC_PTR] = R1;
SSYNC;
//Enable PPI DMA
//small desc list, NDSIZE=3,
//DI_EN, RESTART, DMA1D,
//16bit transfer, memory write, DMAEN
R7.L = 0x6397;
W[P0+DMA0_CONFIG-DMA0_NEXT_DESC_PTR] = R7;
SSYNC;
NOP;
(R7:0,P5:0)=[SP++];
RETS=[SP++];
_ppi_dma_en.end:
RTS;
.global _ppi_dma_disable;
_ppi_dma_disable:
[--SP]=RETS;
[--SP] = (R7:0, P5:0);
p0.h = HI(DMA0_NEXT_DESC_PTR);
p0.l = LO(DMA0_NEXT_DESC_PTR);
r7 = 0;
w[p0+DMA0_CONFIG-DMA0_NEXT_DESC_PTR] = r7;
ssync;
NOP;
NOP;
NOP;
(R7:0,P5:0)=[SP++];
RETS=[SP++];
RTS;
_ppi_dma_disable.end:
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